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nb/intel/nehalem: Change the output verbosity of raminit timings

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This decreases the output verbosity of RAM_DEBUG to be useful.

Change-Id: I9fa681303da0e063dd2ca789d7711151b2365f16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-10-14 19:05:14 +02:00 committed by Patrick Georgi
parent 04b5123aed
commit c892db6398
1 changed files with 11 additions and 11 deletions
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22
src/northbridge/intel/nehalem/raminit.c
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@ -1576,14 +1576,14 @@ static void write_training_data(struct raminfo *info)
static void dump_timings(struct raminfo *info) static void dump_timings(struct raminfo *info)
{ {
int channel, slot, rank, lane, i; int channel, slot, rank, lane, i;
printk(RAM_DEBUG, "Timings:\n"); printk(RAM_SPEW, "Timings:\n");
FOR_POPULATED_RANKS { FOR_POPULATED_RANKS {
printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel, printk(RAM_SPEW, "channel %d, slot %d, rank %d\n", channel,
slot, rank); slot, rank);
for (lane = 0; lane < 9; lane++) { for (lane = 0; lane < 9; lane++) {
printk(RAM_DEBUG, "lane %d: ", lane); printk(RAM_SPEW, "lane %d: ", lane);
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
printk(RAM_DEBUG, "%x (%x) ", printk(RAM_SPEW, "%x (%x) ",
read_500(info, channel, read_500(info, channel,
get_timing_register_addr get_timing_register_addr
(lane, i, slot, rank), (lane, i, slot, rank),
@ -1592,12 +1592,12 @@ static void dump_timings(struct raminfo *info)
lane_timings[i][channel][slot][rank] lane_timings[i][channel][slot][rank]
[lane]); [lane]);
} }
printk(RAM_DEBUG, "\n"); printk(RAM_SPEW, "\n");
} }
} }
printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), printk(RAM_SPEW, "[178] = %x (%x)\n", read_1d0(0x178, 7),
info->training.reg_178); info->training.reg_178);
printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), printk(RAM_SPEW, "[10b] = %x (%x)\n", read_1d0(0x10b, 6),
info->training.reg_10b); info->training.reg_10b);
} }
@ -4011,19 +4011,19 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
int j; int j;
if (s3resume && info.cached_training) { if (s3resume && info.cached_training) {
restore_274265(&info); restore_274265(&info);
printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", printk(RAM_SPEW, "reg2ca9_bit0 = %x\n",
info.cached_training->reg2ca9_bit0); info.cached_training->reg2ca9_bit0);
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++)
for (j = 0; j < 3; j++) for (j = 0; j < 3; j++)
printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", printk(RAM_SPEW, "reg274265[%d][%d] = %x\n",
i, j, info.cached_training->reg274265[i][j]); i, j, info.cached_training->reg274265[i][j]);
} else { } else {
set_274265(&info); set_274265(&info);
printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", printk(RAM_SPEW, "reg2ca9_bit0 = %x\n",
info.training.reg2ca9_bit0); info.training.reg2ca9_bit0);
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++)
for (j = 0; j < 3; j++) for (j = 0; j < 3; j++)
printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", printk(RAM_SPEW, "reg274265[%d][%d] = %x\n",
i, j, info.training.reg274265[i][j]); i, j, info.training.reg274265[i][j]);
} }