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soc/intel/cannonlake: Add processor power limits control support

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Add processor power limits control support to configure values.

BRANCH=None
BUG=b:122343940
TEST=Built and tested on Arcada system

Change-Id: I5990dc05b51481a0074855914cef20cf07378cde
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Sumeet Pawnikar
2019-01-08 19:52:54 +05:30
committed by Patrick Georgi
parent e97e90959c
commit c896e92eaa
4 changed files with 220 additions and 0 deletions
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14
src/soc/intel/cannonlake/chip.h
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@@ -197,8 +197,22 @@ struct soc_intel_cannonlake_config {
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
/* PL1 Override value in Watts */
uint32_t tdp_pl1_override;
/* PL2 Override value in Watts */
uint32_t tdp_pl2_override;
/* SysPL2 Value in Watts */
uint32_t tdp_psyspl2;
/* SysPL3 Value in Watts */
uint32_t tdp_psyspl3;
/* SysPL3 window size */
uint32_t tdp_psyspl3_time;
/* SysPL3 duty cycle */
uint32_t tdp_psyspl3_dutycycle;
/* PL4 Value in Watts */
uint32_t tdp_pl4;
/* Intel Speed Shift Technology */
uint8_t speed_shift_enable;
/* Enable VR specific mailbox command