Reland "Kconfig: Bring HEAP_SIZE to a common, large value"

This reverts commit acbc491237.

Reason for revert: CB:79525 fixes the issue that led to the revert
by not maintaining the heap in the SMM-stored copy of ramstage at all.

Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Georgi
2024-01-16 17:04:55 +00:00
committed by Subrata Banik
parent 01bad20fab
commit c8a695550f
21 changed files with 1 additions and 82 deletions

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@ -759,8 +759,7 @@ config RTC
config HEAP_SIZE config HEAP_SIZE
hex hex
default 0x100000 if FLATTENED_DEVICE_TREE default 0x100000
default 0x4000
config STACK_SIZE config STACK_SIZE
hex hex

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@ -35,7 +35,4 @@ config MAX_CPUS
default 32 if SMM_TSEG default 32 if SMM_TSEG
default 4 default 4
config HEAP_SIZE
default 0x8000
endif endif

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@ -10,9 +10,6 @@ config BOARD_SPECIFIC_OPTIONS
select FLATTENED_DEVICE_TREE select FLATTENED_DEVICE_TREE
select SPI_SDCARD select SPI_SDCARD
config HEAP_SIZE
default 0x10000
config MAINBOARD_DIR config MAINBOARD_DIR
default "sifive/hifive-unleashed" default "sifive/hifive-unleashed"

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@ -25,8 +25,4 @@ config S3_VGA_ROM_RUN
source "src/northbridge/amd/pi/00730F01/Kconfig" source "src/northbridge/amd/pi/00730F01/Kconfig"
config HEAP_SIZE
hex
default 0xc0000
endif # NORTHBRIDGE_AMD_PI endif # NORTHBRIDGE_AMD_PI

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@ -182,11 +182,6 @@ config SMM_TSEG_SIZE
hex hex
default 0x800000 default 0x800000
#TODO: Check if the value of HEAP_SIZE is optimal
config HEAP_SIZE
hex
default 0x200000
config ACPI_SSDT_PSD_INDEPENDENT config ACPI_SSDT_PSD_INDEPENDENT
bool "Allow core p-state independent transitions" bool "Allow core p-state independent transitions"
default y default y

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@ -266,10 +266,6 @@ config S3_VGA_ROM_RUN
bool bool
default n default n
config HEAP_SIZE
hex
default 0xc0000
config SERIRQ_CONTINUOUS_MODE config SERIRQ_CONTINUOUS_MODE
bool bool
default n default n

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@ -158,10 +158,6 @@ config S3_VGA_ROM_RUN
bool bool
default n default n
config HEAP_SIZE
hex
default 0xc0000
config EHCI_BAR config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000

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@ -30,9 +30,6 @@ config ARCH_ARMV8_EXTENSION
int int
default 1 default 1
config HEAP_SIZE
default 0x10000
config STACK_SIZE config STACK_SIZE
default 0x2000 default 0x2000

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@ -216,11 +216,6 @@ config IED_REGION_SIZE
hex hex
default 0x400000 default 0x400000
config HEAP_SIZE
hex
default 0x80000 if BMP_LOGO
default 0x10000
config GFX_GMA_DEFAULT_MMIO config GFX_GMA_DEFAULT_MMIO
default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT

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@ -255,10 +255,6 @@ config IFWI_FILE_NAME
help help
Name of file to store in the IFWI region. Name of file to store in the IFWI region.
config HEAP_SIZE
hex
default 0x8000
config MAX_ROOT_PORTS config MAX_ROOT_PORTS
int int
default 6 default 6

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@ -177,10 +177,6 @@ config IED_REGION_SIZE
hex hex
default 0x400000 default 0x400000
config HEAP_SIZE
hex
default 0x8000
config NHLT_DMIC_1CH_16B config NHLT_DMIC_1CH_16B
bool bool
depends on ACPI_NHLT depends on ACPI_NHLT

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@ -104,10 +104,6 @@ config IED_REGION_SIZE
hex hex
default 0x0 default 0x0
config HEAP_SIZE
hex
default 0x8000
config MAX_ROOT_PORTS config MAX_ROOT_PORTS
int int
default 7 default 7

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@ -106,10 +106,6 @@ config IED_REGION_SIZE
hex hex
default 0x400000 default 0x400000
config HEAP_SIZE
hex
default 0x8000
config MAX_ROOT_PORTS config MAX_ROOT_PORTS
int int
default 8 default 8

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@ -199,11 +199,6 @@ config IED_REGION_SIZE
hex hex
default 0x400000 default 0x400000
config HEAP_SIZE
hex
default 0x80000 if BMP_LOGO
default 0x10000
# Intel recommends reserving the PCIe TBT root port resources as below: # Intel recommends reserving the PCIe TBT root port resources as below:
# - 42 buses # - 42 buses
# - 194 MiB Non-prefetchable memory # - 194 MiB Non-prefetchable memory

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@ -151,10 +151,6 @@ config EXCLUDE_NATIVE_SD_INTERFACE
help help
If you set this option to n, will not use native SD controller. If you set this option to n, will not use native SD controller.
config HEAP_SIZE
hex
default 0x80000
config IED_REGION_SIZE config IED_REGION_SIZE
hex hex
default 0x400000 default 0x400000

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@ -152,10 +152,6 @@ config IED_REGION_SIZE
config INTEL_TME config INTEL_TME
default n default n
config HEAP_SIZE
hex
default 0x10000
config MAX_ROOT_PORTS config MAX_ROOT_PORTS
int int
default 24 if SOC_INTEL_TIGERLAKE_PCH_H default 24 if SOC_INTEL_TIGERLAKE_PCH_H

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@ -94,10 +94,6 @@ config ECAM_MMCONF_BUS_NUMBER
config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION
default y default y
config HEAP_SIZE
hex
default 0x80000
config HPET_MIN_TICKS config HPET_MIN_TICKS
hex hex
default 0x80 default 0x80

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@ -71,10 +71,6 @@ config CPU_MICROCODE_CBFS_LEN
hex hex
default 0x7C00 default 0x7C00
config HEAP_SIZE
hex
default 0x80000
config STACK_SIZE config STACK_SIZE
hex hex
default 0x4000 default 0x4000

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@ -55,10 +55,6 @@ config CPU_MICROCODE_CBFS_LEN
hex hex
default 0x7C00 default 0x7C00
config HEAP_SIZE
hex
default 0x80000
config IED_REGION_SIZE config IED_REGION_SIZE
hex hex
default 0x400000 default 0x400000

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@ -80,10 +80,6 @@ config CPU_MICROCODE_CBFS_LEN
hex hex
default 0x8c00 default 0x8c00
config HEAP_SIZE
hex
default 0x80000
config STACK_SIZE config STACK_SIZE
hex hex
default 0x4000 default 0x4000

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@ -57,8 +57,4 @@ config SBL_UTIL_PATH
help help
Path for utils to combine SBL_ELF and bootblock Path for utils to combine SBL_ELF and bootblock
config HEAP_SIZE
hex
default 0x8000
endif endif