soc/intel/cannonlake: Define Max PCIE Root Ports

This patch defines Max PCIE Root Ports and fixes
bellow Coverity scan defect,

*** CID 1380036:  Control flow issues  (NO_EFFECT)
/src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params()
79
>>>     CID 1380036:  Control flow issues  (NO_EFFECT)
>>>     "i" is converted to an unsigned type because it's compared to an unsigned constant.
80      for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
81              if (config->PcieRpEnable[i])
82                      mask |= (1 << i);

Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/Kconfig

@@ -92,6 +92,10 @@ config IED_REGION_SIZE
 	hex
 	default 0x400000
 
+config MAX_ROOT_PORTS
+	int
+	default 24
+
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000

src/soc/intel/cannonlake/romstage/romstage.c

@@ -68,7 +68,7 @@ asmlinkage void car_stage_entry(void)
 
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 {
-	int i;
+	unsigned int i;
 	uint32_t mask = 0;
 
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;