From c8fc542e1b7828e86e2d4a5b6b743ce7a7d50665 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 3 May 2021 02:31:01 +0200 Subject: [PATCH] soc/intel/jasperlake: Clean up FSP chipset lockdown configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/52845 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/soc/intel/jasperlake/fsp_params.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index d68494f290..bb41b28f15 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -70,17 +70,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); /* Chipset Lockdown */ - if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - params->PchLockDownGlobalSmi = 0; - params->PchLockDownBiosInterface = 0; - params->PchUnlockGpioPads = 1; - params->RtcMemoryLock = 0; - } else { - params->PchLockDownGlobalSmi = 1; - params->PchLockDownBiosInterface = 1; - params->PchUnlockGpioPads = 0; - params->RtcMemoryLock = 1; - } + const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; + params->PchLockDownGlobalSmi = lockdown_by_fsp; + params->PchLockDownBiosInterface = lockdown_by_fsp; + params->PchUnlockGpioPads = !lockdown_by_fsp; + params->RtcMemoryLock = lockdown_by_fsp; /* coreboot will send EOP before loading payload */ params->EndOfPostMessage = EOP_DISABLE;