sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/poppy/variants/atlas: DPTF tuning v2

Browse Source 
We have more test data now so update the DPTF accordingly.
* Change passive temp to 50/57/55/52 C
* Change critical temp to 75C
* All interval to 20 secs

BUG=b:113101335
TEST=temp/perf looks better in thermal chamber test.

Change-Id: I872c3f1875d0cbac148c44c449954e6871c9d0b0
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Puthikorn Voravootivat
2019-03-12 15:56:00 -07:00
committed by Patrick Georgi
parent 42a66fb721
commit c912f76486
1 changed files with 13 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl
View File

@@ -19,22 +19,22 @@
#define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "Ambient"
#define DPTF_TSR0_PASSIVE 48
#define DPTF_TSR0_CRITICAL 90
#define DPTF_TSR0_PASSIVE 50
#define DPTF_TSR0_CRITICAL 75
#define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "Charger"
#define DPTF_TSR1_PASSIVE 53
#define DPTF_TSR1_CRITICAL 90
#define DPTF_TSR1_PASSIVE 57
#define DPTF_TSR1_CRITICAL 75
#define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "DRAM"
#define DPTF_TSR2_PASSIVE 54
#define DPTF_TSR2_PASSIVE 55
#define DPTF_TSR2_CRITICAL 75
#define DPTF_TSR3_SENSOR_ID 4
#define DPTF_TSR3_SENSOR_NAME "eMMC"
#define DPTF_TSR3_PASSIVE 54
#define DPTF_TSR3_PASSIVE 52
#define DPTF_TSR3_CRITICAL 75
#undef DPTF_ENABLE_FAN_CONTROL
@@ -53,25 +53,25 @@ Name (DTRT, Package () {
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 200, 0, 0, 0, 0 },
/* CPU Throttle Effect on DRAM */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 200, 0, 0, 0, 0 },
/* CPU Throttle Effect on eMMC */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 200, 0, 0, 0, 0 },
/* Charger Throttle Effect on Ambient */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 200, 50, 0, 0, 0, 0 },
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 200, 200, 0, 0, 0, 0 },
/* Charger Throttle Effect on Charger */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 50, 0, 0, 0, 0 },
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 200, 0, 0, 0, 0 },
/* Charger Throttle Effect on DRAM */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 50, 0, 0, 0, 0 },
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 200, 0, 0, 0, 0 },
/* Charger Throttle Effect on eMMC */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 200, 50, 0, 0, 0, 0 },
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 200, 200, 0, 0, 0, 0 },
})
Name (MPPC, Package ()