mb/framework: Push initial port of azalea (Framework 13 AMD 7040)

This is a minimal framework that allows the build to compile.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ief4b5c75471a2ef5bedaaee9b4737510c2826b6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

src/mainboard/framework/Kconfig

@@ -0,0 +1,17 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+if VENDOR_FRAMEWORK
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/framework/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/framework/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "Framework"
+
+endif # VENDOR_FRAMEWORK

src/mainboard/framework/Kconfig.name

@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+config VENDOR_FRAMEWORK
+	bool "Framework"

src/mainboard/framework/azalea/Kconfig

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_FRAMEWORK_AZALEA
+	select BOARD_ROMSIZE_KB_32768
+	select SOC_AMD_PHOENIX_FSP
+
+if BOARD_FRAMEWORK_AZALEA
+
+config MAINBOARD_DIR
+	default "framework/azalea"
+
+config MAINBOARD_PART_NUMBER
+	default "Azalea"
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/coreboot.fmd"
+
+endif

src/mainboard/framework/azalea/Kconfig.name

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_FRAMEWORK_AZALEA
+	bool "Azalea (Framework 13 AMD 7040)"

src/mainboard/framework/azalea/Makefile.mk

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += port_descriptors.c
+
+ramstage-y += mainboard.c
+ramstage-y += port_descriptors.c

src/mainboard/framework/azalea/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Framework
+Board name: Azalea (13" AMD Ryzen 7040)
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n

src/mainboard/framework/azalea/bootblock.c

@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+
+void bootblock_mainboard_early_init(void)
+{
+}

src/mainboard/framework/azalea/coreboot.fmd

@@ -0,0 +1,12 @@
+FLASH@0xFF000000 32M {
+	BIOS_PAGE_1 16M {
+		FMAP 4K
+		COREBOOT(CBFS)
+		SMMSTORE(PRESERVE) 64K
+		RW_MRC_CACHE 256K
+		RECOVERY_MRC_CACHE(PRESERVE) 256K
+	}
+	BIOS_PAGE_2 16M {
+		UNUSED
+	}
+}

src/mainboard/framework/azalea/devicetree.cb

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/amd/phoenix
+
+	device domain 0 on
+	end # domain
+
+end	# chip soc/amd/phoenix

src/mainboard/framework/azalea/dsdt.asl

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock (
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x00010001	/* OEM Revision */
+)
+{
+	#include <acpi/dsdt_top.asl>
+}

src/mainboard/framework/azalea/mainboard.c

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/amd_pci_util.h>
+#include <device/device.h>
+
+/*
+ * This controls the device -> IRQ routing.
+ *
+ */
+static const struct fch_irq_routing fch_irq_map[] = {
+};
+
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+{
+	*length = ARRAY_SIZE(fch_irq_map);
+	return fch_irq_map;
+}
+
+static void mainboard_init(void *chip_info)
+{
+}
+
+static void mainboard_enable(struct device *dev)
+{
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};

src/mainboard/framework/azalea/port_descriptors.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/platform_descriptors.h>
+
+void mainboard_get_dxio_ddi_descriptors(
+		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
+		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
+{
+}

src/mainboard/framework/azalea/romstage.c

@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */

src/mainboard/framework/azalea/smihandler.c

@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */