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soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init

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FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize
& tear down Cache-As-Ram.  Add TempRamInit & TempRamExit usage to
ApolloLake SoC when CONFIG_FSP_CAR is enabled.

Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.

Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17063
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Brenton Dong
2016-10-18 13:57:54 -07:00
committed by Martin Roth
parent 0a5971c91b
commit c9b398191e
4 changed files with 173 additions and 4 deletions
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5
src/arch/x86/exit_car.S
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@ -19,7 +19,8 @@
.section ".module_parameters", "aw", @progbits
/* stack_top indicates the stack to pull MTRR information from. */
stack_top:
.global post_car_stack_top
post_car_stack_top:
.long 0
.long 0
@ -38,7 +39,7 @@ _start:
invd
/* Set up new stack. */
mov stack_top, %esp
mov post_car_stack_top, %esp
/*
* Honor variable MTRR information pushed on the stack with the