From c9d9c491ece103670346aff41b25f59b52260333 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Mon, 23 Nov 2020 20:50:44 -0700
Subject: [PATCH] Also require TBT0 and TBT1 resource for DMA and RP

Change-Id: I6238c0b6cb7b47c18f3918d53f0e5c1a6706ce57
---
 src/soc/intel/tigerlake/acpi/tcss_dma.asl    | 12 ++++++++++--
 src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 12 ++++++++++--
 2 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
index 085990dbfd..e3d66f642f 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
@@ -32,12 +32,20 @@ Method (_S0W, 0x0)
 
 Method (_PR0)
 {
-	Return (Package() { \_SB.PCI0.D3C })
+	If (DUID == 0) {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
+	} Else {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
+	}
 }
 
 Method (_PR3)
 {
-	Return (Package() { \_SB.PCI0.D3C })
+	If (DUID == 0) {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
+	} Else {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
+	}
 }
 
 /*
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
index 08d890087c..9e1b324bfe 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
@@ -227,12 +227,20 @@ Method (_S0W, 0x0, NotSerialized)
 
 Method (_PR0)
 {
-	Return (Package() { \_SB.PCI0.D3C })
+	If ((TUID == 0) || (TUID == 1)) {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
+	} Else {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
+	}
 }
 
 Method (_PR3)
 {
-	Return (Package() { \_SB.PCI0.D3C })
+	If ((TUID == 0) || (TUID == 1)) {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
+	} Else {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
+	}
 }
 
 /*