nb/intel/gm45: Remove UMA alignment optimization

This code path was only triggered in one corner case: GFX UMA set to
48MiB. It created a hole below UMA to save MTRRs. But, this hole was
never accounted for when calculating cbmem_top(). Instead of trying
to fix it, remove it, it's not worth the trouble.

TEST=Booted lenovo/x200 with all available CMOS gfx_uma_size settings.

Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/gm45/raminit.c

@@ -1241,10 +1241,6 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode
 			printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
 
 			uma_sizem = (gms_sizek + gsm_sizek) >> 10;
-			/* Further reduce MTRR usage if it costs use less than
-			   16 MiB.  */
-			if (ALIGN_UP(uma_sizem, 64) - uma_sizem <= 16)
-				uma_sizem = ALIGN_UP(uma_sizem, 64);
 		}
 	}