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soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree

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The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the
equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set.
Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD
as well for Alder Lake.

Setting this FSP-M UPD will cause FSP to properly program sideband
use BSSB_LSx pins for the enabled Type-C ports. Required for proper
DCI debug and TCSS initialization flow.

Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80500
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Michał Żygowski
2024-02-14 13:23:28 +01:00
committed by Felix Singer
parent f0fb3af828
commit ca5254acc0
1 changed files with 5 additions and 0 deletions
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5
src/soc/intel/alderlake/romstage/fsp_params.c
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@@ -271,6 +271,11 @@ static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg,
m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0);
m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1);
m_cfg->UsbTcPortEnPreMem = 0;
for (int i = 0; i < MAX_TYPE_C_PORTS; i++)
if (config->tcss_ports[i].enable)
m_cfg->UsbTcPortEnPreMem |= BIT(i);
#if (CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)) || \
(!CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) && CONFIG(FSP_USE_REPO))
m_cfg->DisableDynamicTccoldHandshake =