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libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2

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This patch adds the new, faster architectural register accessors to
libpayload that were already added to coreboot in CB:27881. It also
hardcodes the assumption that coreboot payloads run at EL2, which has
already been hardcoded in coreboot with CB:27880 (see rationale there).
This means we can drop all the read_current/write_current stuff which
added a lot of unnecessary helpers to check the current exception level.

This patch breaks payloads that used read_current/write_current
accessors, but it seems unlikely that many payloads deal with this stuff
anyway, and it should be a trivial fix (just replace them with the
respective _el2 versions).

Also add accessors for a couple of more registers that are required to
enable debug mode while I'm here.

Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Julius Werner
2018-10-10 15:31:36 -07:00
parent e1b1ec7154
commit ca52a25882
13 changed files with 244 additions and 2155 deletions
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4
payloads/libpayload/arch/arm64/exception.c
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@ -81,8 +81,8 @@ static void print_regs(struct exception_state *state)
printf("ELR = 0x%016llx ESR = 0x%08llx\n",
state->elr, state->esr);
printf("FAR = 0x%016llx SPSR = 0x%08x\n",
raw_read_far_current(), raw_read_spsr_current());
printf("FAR = 0x%016llx SPSR = 0x%08llx\n",
raw_read_far_el2(), raw_read_spsr_el2());
for (i = 0; i < 30; i += 2) {
printf("X%02d = 0x%016llx X%02d = 0x%016llx\n",
i, state->regs[i], i + 1, state->regs[i + 1]);