libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2
This patch adds the new, faster architectural register accessors to libpayload that were already added to coreboot in CB:27881. It also hardcodes the assumption that coreboot payloads run at EL2, which has already been hardcoded in coreboot with CB:27880 (see rationale there). This means we can drop all the read_current/write_current stuff which added a lot of unnecessary helpers to check the current exception level. This patch breaks payloads that used read_current/write_current accessors, but it seems unlikely that many payloads deal with this stuff anyway, and it should be a trivial fix (just replace them with the respective _el2 versions). Also add accessors for a couple of more registers that are required to enable debug mode while I'm here. Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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@@ -27,11 +27,6 @@
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* SUCH DAMAGE.
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*/
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#define __ASSEMBLY__
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#include <arch/lib_helpers.h>
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.text
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/* Macro for exception entry
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* Store x30 before any branch
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* Branch to exception_prologue to save rest of the registers
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@@ -92,10 +87,10 @@ exception_prologue:
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stp x0, x1, [sp, #-16]!
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/* Save the exception reason on stack */
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read_current x1, esr
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mrs x1, esr_el2
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/* Save the return address on stack */
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read_current x0, elr
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mrs x0, elr_el2
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stp x0, x1, [sp, #-16]!
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ret
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@@ -109,8 +104,8 @@ exception_handler:
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/* Pop return address saved on stack */
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ldp x0, x1, [sp], #16
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write_current elr, x0, x2
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write_current esr, x1, x2
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msr elr_el2, x0
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msr esr_el2, x1
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/* Pop exception reason saved on stack, followed by regs x0-x30 */
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ldp x0, x1, [sp], #16
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ldp x2, x3, [sp], #16
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@@ -132,5 +127,5 @@ exception_handler:
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.global set_vbar
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set_vbar:
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write_current vbar, x0, x1
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msr vbar_el2, x0
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ret
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