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CBMEM intel: Define get_top_of_ram() once per chipset

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Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.

Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.

Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki
2013-10-15 17:19:41 +03:00
parent bbf013c38f
commit cb08e169cf
11 changed files with 129 additions and 67 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/i945/Makefile.inc
View File

@@ -17,10 +17,12 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
romstage-y += ram_calc.c
romstage-y += raminit.c
romstage-y += early_init.c
romstage-y += errata.c

57
src/northbridge/intel/i945/ram_calc.c Normal file
View File

@@ -0,0 +1,57 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// Use simple device model for this file even in ramstage
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cbmem.h>
#include "i945.h"
unsigned long get_top_of_ram(void)
{
u32 tom;
if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) {
/* IGD enabled, get top of Memory from BSM register */
tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
} else {
tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
}
/* if TSEG enabled subtract size */
switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) {
case 0x01:
/* 1MB TSEG */
tom -= 0x10000;
break;
case 0x03:
/* 2MB TSEG */
tom -= 0x20000;
break;
case 0x05:
/* 8MB TSEG */
tom -= 0x80000;
break;
default:
/* TSEG either disabled or invalid */
break;
}
return (unsigned long) tom;
}

33
src/northbridge/intel/i945/raminit.c
View File

@@ -3183,36 +3183,3 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
sdram_setup_processor_side();
}
unsigned long get_top_of_ram(void)
{
u32 tom;
if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) {
/* IGD enabled, get top of Memory from BSM register */
tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
} else {
tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
}
/* if TSEG enabled subtract size */
switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) {
case 0x01:
/* 1MB TSEG */
tom -= 0x10000;
break;
case 0x03:
/* 2MB TSEG */
tom -= 0x20000;
break;
case 0x05:
/* 8MB TSEG */
tom -= 0x80000;
break;
default:
/* TSEG either disabled or invalid */
break;
}
return (unsigned long) tom;
}