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util/inteltool: Add more Westmere/Ironlake device IDs

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The host bridge PCI device ID can be changed by the firmware. There
is no documentation about it, though. There's 'official' IDs, which
appear in spec updates and Windows drivers, and 'mysterious' IDs,
which Intel doesn't want OSes to know about and thus are not listed.

For the sake of completeness, add the PCI device IDs for Clarkdale.
Though coreboot only supports Arrandale, both of them are Ironlake.

It is possible that the Management Engine handles changing the PCI
device ID, which would not happen when using a broken ME firmware.

Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
2021-12-18 17:38:32 +01:00
committed by Nico Huber
parent d20cc994ba
commit cb125d6f94
4 changed files with 17 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
util/inteltool/inteltool.c
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@ -81,7 +81,11 @@ static const struct {
/* Host bridges /DRAM controllers integrated in CPUs */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN,
"0th generation (Nehalem family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN,
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D,
"1st generation (Westmere family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M,
"1st generation (Westmere family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048,
"1st generation (Westmere family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D,
"2nd generation (Sandy Bridge family) Core Processor (Desktop)" },

4
util/inteltool/inteltool.h
View File

@ -346,7 +346,9 @@ static inline uint32_t inl(unsigned port)
/* Intel starts counting these generations with the integration of the DRAM controller */
#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D 0x0040 /* Clarkdale (Westmere Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M 0x0044 /* Arrandale (Westmere Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048 0x0048 /* Unknown Westmere */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */

8
util/inteltool/memory.c
View File

@ -192,7 +192,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
break;
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048:
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
@ -266,7 +268,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
switch (nb->device_id)
{
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048:
printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
dump_timings ();
if (dump_spd_file != NULL)

4
util/inteltool/pcie.c
View File

@ -378,7 +378,9 @@ int print_dmibar(struct pci_dev *nb)
dmi_registers = nehalem_dmi_registers;
size = ARRAY_SIZE(nehalem_dmi_registers);
break;
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048:
dmibar_phys = pci_read_long(nb, 0x68);
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */