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inteltool: Add southbridge and CPU definitions for Skylake

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Change-Id: Id9501f11a79cb314bc407760b22006a3375e669d
Signed-off-by: Maximilian Schander <maxschander@googlemail.com>
Reviewed-on: https://review.coreboot.org/22211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Maximilian Schander
2017-10-28 14:45:48 +02:00
committed by Martin Roth
parent 8890dccb23
commit cb2d21d24d
2 changed files with 34 additions and 1 deletions
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15
util/inteltool/inteltool.h
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@ -139,7 +139,21 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141
#define PCI_DEVICE_ID_INTEL_H110 0xa143
#define PCI_DEVICE_ID_INTEL_H170 0xa144
#define PCI_DEVICE_ID_INTEL_Z170 0xa145
#define PCI_DEVICE_ID_INTEL_Q170 0xa146
#define PCI_DEVICE_ID_INTEL_Q150 0xa147
#define PCI_DEVICE_ID_INTEL_B150 0xa148
#define PCI_DEVICE_ID_INTEL_C236 0xa149
#define PCI_DEVICE_ID_INTEL_C232 0xa14a
#define PCI_DEVICE_ID_INTEL_QM170 0xa14d
#define PCI_DEVICE_ID_INTEL_HM170 0xa14e
#define PCI_DEVICE_ID_INTEL_CM236 0xa150
#define PCI_DEVICE_ID_INTEL_HM175 0xa152
#define PCI_DEVICE_ID_INTEL_QM175 0xa153
#define PCI_DEVICE_ID_INTEL_CM238 0xa154
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
@ -208,6 +222,7 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918
#if !defined(__DARWIN__) && !defined(__FreeBSD__)