add framework for i440bx chipset
add support for NSC pc87351 SuperIO add Bitworks/IMS manboard config This is a very basic framework for the i440bx chipset and the Bitworks IMS board that uses it. Most things are structure only. Known issues: - SMbus reads to the RAM SPD come back all zero. - dump_spd_registers() is commented out since it breaks with the default setting of generic_dump_spd.c where it wants 2 memory controllers. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Richard Smith
399
src/northbridge/intel/i440bx/raminit.c
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399
src/northbridge/intel/i440bx/raminit.c
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#include <cpu/x86/mtrr.h>
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#include "raminit.h"
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/*
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This software and ancillary information (herein called SOFTWARE )
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called LinuxBIOS is made available under the terms described
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here. The SOFTWARE has been approved for release with associated
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LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
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been authored by an employee or employees of the University of
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California, operator of the Los Alamos National Laboratory under
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Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
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U.S. Government has rights to use, reproduce, and distribute this
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SOFTWARE. The public may copy, distribute, prepare derivative works
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and publicly display this SOFTWARE without charge, provided that this
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Notice and any statement of authorship are reproduced on all copies.
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Neither the Government nor the University makes any warranty, express
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or implied, or assumes any liability or responsibility for the use of
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this SOFTWARE. If SOFTWARE is modified to produce derivative works,
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such modified SOFTWARE should be clearly marked, so as not to confuse
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it with the version available from LANL.
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*/
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/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
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* rminnich@lanl.gov
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*/
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/*
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* 11/26/02 - kevinh@ispiri.com - The existing comments implied that
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* this didn't work yet. Therefore, I've updated it so that it works
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* correctly - at least on my VIA epia motherboard. 64MB DIMM in slot 0.
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*/
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/* Added automatic detection of first equipped bank and its MA mapping type.
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* (Rest of configuration is done in C)
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* 5/19/03 by SONE Takeshi <ts1@tsn.or.jp>
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*/
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/* converted to C 9/2003 Ron Minnich */
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/* Modified for the i440bx Richard Smith 01/2005 */
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/* Set to 1 if your DIMMs are PC133 Note that I'm assuming CPU's FSB
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* frequency is 133MHz. If your CPU runs at another bus speed, you
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* might need to change some of register values.
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*/
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#ifndef DIMM_PC133
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#define DIMM_PC133 0
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#endif
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// Set to 1 if your DIMMs are CL=2
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#ifndef DIMM_CL2
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#define DIMM_CL2 0
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#endif
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void dimms_read(unsigned long x)
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{
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uint8_t c;
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unsigned long eax;
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volatile unsigned long y;
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eax = x;
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for(c = 0; c < 6; c++) {
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y = * (volatile unsigned long *) eax;
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eax += 0x10000000;
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}
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}
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void dimms_write(int x)
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{
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uint8_t c;
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unsigned long eax = x;
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for(c = 0; c < 6; c++) {
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*(volatile unsigned long *) eax = 0;
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eax += 0x10000000;
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}
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}
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#ifdef DEBUG_SETNORTHB
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void setnorthb(device_t north, uint8_t reg, uint8_t val)
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{
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print_debug("setnorth: reg ");
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print_debug_hex8(reg);
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print_debug(" to ");
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print_debug_hex8(val);
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print_debug("\r\n");
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pci_write_config8(north, reg, val);
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}
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#else
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#define setnorthb pci_write_config8
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#endif
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void
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dumpnorth(device_t north)
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{
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unsigned int r, c;
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for(r = 0; ; r += 16) {
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print_debug_hex8(r);
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print_debug(":");
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for(c = 0; c < 16; c++) {
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print_debug_hex8(pci_read_config8(north, r+c));
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print_debug(" ");
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}
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print_debug("\r\n");
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if (r >= 240)
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break;
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}
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}
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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device_t north = (device_t) 0;
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uint8_t c, r;
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print_err("vt8601 init starting\r\n");
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north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
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north = 0;
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print_debug_hex32(north);
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print_debug(" is the north\n");
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print_debug_hex16(pci_read_config16(north, 0));
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print_debug(" ");
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print_debug_hex16(pci_read_config16(north, 2));
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print_debug("\r\n");
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/* All we are doing now is setting initial known-good values that will
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* be revised later as we read SPD
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*/
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// memory clk enable. We are not using ECC
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pci_write_config8(north,0x78, 0x01);
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print_debug_hex8(pci_read_config8(north, 0x78));
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// dram control, see the book.
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#if DIMM_PC133
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pci_write_config8(north,0x68, 0x52);
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#else
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pci_write_config8(north,0x68, 0x42);
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#endif
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// dram control, see the book.
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pci_write_config8(north,0x6B, 0x0c);
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// Initial setting, 256MB in each bank, will be rewritten later.
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pci_write_config8(north,0x5A, 0x20);
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print_debug_hex8(pci_read_config8(north, 0x5a));
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pci_write_config8(north,0x5B, 0x40);
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pci_write_config8(north,0x5C, 0x60);
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pci_write_config8(north,0x5D, 0x80);
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pci_write_config8(north,0x5E, 0xA0);
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pci_write_config8(north,0x5F, 0xC0);
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// It seems we have to take care of these 2 registers as if
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// they are bank 6 and 7.
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pci_write_config8(north,0x56, 0xC0);
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pci_write_config8(north,0x57, 0xC0);
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// SDRAM in all banks
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pci_write_config8(north,0x60, 0x3F);
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// DRAM timing. I'm suspicious of this
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// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
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// ras precharge 4T, RAS pulse 5T
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// cas2 is 0xd6, cas3 is 0xe6
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// we're also backing off write pulse width to 2T, so result is 0xee
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#if DIMM_CL2
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pci_write_config8(north,0x64, 0xd4);
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pci_write_config8(north,0x65, 0xd4);
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pci_write_config8(north,0x66, 0xd4);
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#else // CL=3
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pci_write_config8(north,0x64, 0xe4);
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pci_write_config8(north,0x65, 0xe4);
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pci_write_config8(north,0x66, 0xe4);
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#endif
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// dram frequency select.
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// enable 4K pages for 64M dram.
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#if DIMM_PC133
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pci_write_config8(north,0x69, 0x3c);
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#else
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pci_write_config8(north,0x69, 0xac);
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#endif
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/* IMPORTANT -- disable refresh counter */
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// refresh counter, disabled.
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pci_write_config8(north,0x6A, 0x00);
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// clkenable configuration. kevinh FIXME - add precharge
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pci_write_config8(north,0x6C, 0x00);
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// dram read latch delay of 1 ns, MD drive 8 mA,
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// high drive strength on MA[2: 13], we#, cas#, ras#
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// As per Cindy Lee, set to 0x37, not 0x57
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pci_write_config8(north,0x6D, 0x7f);
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}
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/* slot is the dram slot. Return size of side0 in lower 16-bit,
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* side1 in upper 16-bit, in units of 8MB */
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static unsigned long
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spd_module_size(unsigned char slot)
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{
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/* for all the DRAMS, see if they are there and get the size of each
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* module. This is just a very early first cut at sizing.
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*/
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/* we may run out of registers ... */
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unsigned int banks, rows, cols, reg;
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unsigned int value = 0;
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/* unsigned int module = ((0x50 + slot) << 1) + 1; */
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unsigned int module = 0x50 + slot;
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/* is the module there? if byte 2 is not 4, then we'll assume it
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* is useless.
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*/
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print_info("Slot ");
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print_info_hex8(slot);
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if (smbus_read_byte(module, 2) != 4) {
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print_info(" is empty\r\n");
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return 0;
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}
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print_info(" is SDRAM ");
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banks = smbus_read_byte(module, 17);
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/* we're going to assume symmetric banks. Sorry. */
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cols = smbus_read_byte(module, 4) & 0xf;
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rows = smbus_read_byte(module, 3) & 0xf;
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/* grand total. You have rows+cols addressing, * times of banks, times
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* width of data in bytes */
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/* Width is assumed to be 64 bits == 8 bytes */
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value = (1 << (cols + rows)) * banks * 8;
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print_info_hex32(value);
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print_info(" bytes ");
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/* Return in 8MB units */
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value >>= 23;
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/* We should have single or double side */
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if (smbus_read_byte(module, 5) == 2) {
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print_info("x2");
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value = (value << 16) | value;
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}
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print_info("\r\n");
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return value;
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}
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static int
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spd_num_chips(unsigned char slot)
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{
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/* unsigned int module = ((0x50 + slot) << 1) + 1; */
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unsigned int module = 0x50 + slot;
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unsigned int width;
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width = smbus_read_byte(module, 13);
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if (width == 0)
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width = 8;
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return 64 / width;
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}
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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#define T133 7
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unsigned char Trp = 1, Tras = 1, casl = 2, val;
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unsigned char timing = 0xe4;
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/* read Trp */
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val = smbus_read_byte(0x50, 27);
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if (val < 2*T133)
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Trp = 1;
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val = smbus_read_byte(0x50, 30);
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if (val < 5*T133)
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Tras = 0;
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val = smbus_read_byte(0x50, 18);
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if (val < 8)
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casl = 1;
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if (val < 4)
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casl = 0;
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val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
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print_debug_hex8(val); print_debug(" is the computed timing\n");
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/* don't set it. Experience shows that this screwy chipset should just
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* be run with the most conservative timing.
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* pci_write_config8(0, 0x64, val);
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*/
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}
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static void set_ma_mapping(device_t north, int slot, int type)
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{
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unsigned char reg, val;
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int shift;
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reg = 0x58 + slot/2;
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if (slot%2 >= 1)
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shift = 0;
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else
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shift = 4;
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val = pci_read_config8(north, reg);
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val &= ~(0xf << shift);
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val |= type << shift;
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pci_write_config8(north, reg, val);
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}
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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{
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unsigned char i;
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static const uint8_t ramregs[] = {
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0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
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};
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device_t north = 0;
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uint32_t size, base, slot, ma;
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/* begin to initialize*/
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// I forget why we need this, but we do
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dimms_write(0xa55a5aa5);
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/* set NOP*/
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pci_write_config8(north,0x6C, 0x01);
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print_debug("NOP\r\n");
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/* wait 200us*/
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// You need to do the memory reference. That causes the nop cycle.
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dimms_read(0);
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udelay(400);
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print_debug("PRECHARGE\r\n");
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/* set precharge */
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pci_write_config8(north,0x6C, 0x02);
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print_debug("DUMMY READS\r\n");
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/* dummy reads*/
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dimms_read(0);
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udelay(200);
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print_debug("CBR\r\n");
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/* set CBR*/
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pci_write_config8(north,0x6C, 0x04);
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/* do 8 reads and wait >100us between each - from via*/
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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print_debug("MRS\r\n");
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/* set MRS*/
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pci_write_config8(north,0x6c, 0x03);
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#if DIMM_CL2
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dimms_read(0x150);
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#else // CL=3
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dimms_read(0x1d0);
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#endif
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udelay(200);
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print_debug("NORMAL\r\n");
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/* set to normal mode */
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pci_write_config8(north,0x6C, 0x08);
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dimms_write(0x55aa55aa);
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dimms_read(0);
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udelay(200);
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print_debug("set ref. rate\r\n");
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// Set the refresh rate.
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#if DIMM_PC133
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pci_write_config8(north,0x6A, 0x86);
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#else
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pci_write_config8(north,0x6A, 0x65);
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#endif
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print_debug("enable multi-page open\r\n");
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// enable multi-page open
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pci_write_config8(north,0x6B, 0x0d);
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base = 0;
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for(slot = 0; slot < 4; slot++) {
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size = spd_module_size(slot);
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/* side 0 */
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base += size & 0xffff;
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pci_write_config8(north, ramregs[2*slot], base);
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/* side 1 */
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base += size >> 16;
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if (base > 0xff)
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base = 0xff;
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pci_write_config8(north, ramregs[2*slot + 1], base);
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if (!size)
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continue;
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/* Calculate the value of MA mapping type register,
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* based on size of SDRAM chips. */
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size = (size & 0xffff) << (3 + 3);
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/* convert module size to be in Mbits */
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size /= spd_num_chips(slot);
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print_debug_hex16(size);
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print_debug(" is the chip size\r\n");
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if (size < 64)
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ma = 0;
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if (size < 256)
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ma = 8;
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else
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ma = 0xe;
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print_debug_hex16(ma);
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print_debug(" is the MA type\r\n");
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set_ma_mapping(north, slot, ma);
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}
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print_err("vt8601 done\r\n");
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}
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