mb/emulation/qemu-q35: Define and use MMCONF_BUS_NUMBER
Also refactor the machine type checks to avoid code duplication. Tested, still boots to payload with 256, 128 and 64 busses. Change-Id: Ib394ba605bbfeee75aa645e989c23034cceff348 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50025 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -63,6 +63,10 @@ config MAINBOARD_PART_NUMBER
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config MMCONF_BASE_ADDRESS
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config MMCONF_BASE_ADDRESS
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default 0xb0000000
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default 0xb0000000
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config MMCONF_BUS_NUMBER
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int
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default 256
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# fw_cfg tables can be larger than the default when TPM is enabled
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# fw_cfg tables can be larger than the default when TPM is enabled
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config MAX_ACPI_TABLE_SIZE_KB
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config MAX_ACPI_TABLE_SIZE_KB
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int
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int
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@ -1,4 +1,5 @@
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bootblock-y += bootblock.c
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bootblock-y += bootblock.c
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bootblock-y += memmap.c
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romstage-y += ../qemu-i440fx/fw_cfg.c
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romstage-y += ../qemu-i440fx/fw_cfg.c
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romstage-y += ../qemu-i440fx/memmap.c
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romstage-y += ../qemu-i440fx/memmap.c
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@ -10,7 +10,6 @@
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#include "../qemu-i440fx/fw_cfg.h"
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#include "../qemu-i440fx/fw_cfg.h"
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#include "../qemu-i440fx/acpi.h"
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#include "../qemu-i440fx/acpi.h"
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#include "q35.h"
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void mainboard_fill_fadt(acpi_fadt_t *fadt)
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void mainboard_fill_fadt(acpi_fadt_t *fadt)
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{
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{
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@ -40,18 +39,8 @@ unsigned long acpi_fill_madt(unsigned long current)
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unsigned long acpi_fill_mcfg(unsigned long current)
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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{
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struct device *dev;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
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u32 reg;
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CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
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CONFIG_MMCONF_BUS_NUMBER - 1);
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dev = dev_find_device(0x8086, 0x29c0, 0);
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if (!dev)
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return current;
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reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO);
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if ((reg & 0x07) != 0x01) /* require enabled + 256MB size */
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return current;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
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reg & 0xf0000000, 0x0, 0x0, 255);
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return current;
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return current;
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}
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}
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@ -10,8 +10,6 @@
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static void bootblock_northbridge_init(void)
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static void bootblock_northbridge_init(void)
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{
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{
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uint32_t reg;
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/*
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/*
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* The "io" variant of the config access is explicitly used to
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* The "io" variant of the config access is explicitly used to
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* setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
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* setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
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@ -24,16 +22,12 @@ static void bootblock_northbridge_init(void)
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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* 4GiB.
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*/
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*/
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reg = 0;
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const uint32_t pciexbar = make_pciexbar();
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pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_HI, reg);
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pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_HI, 0);
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reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */
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pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, pciexbar);
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pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg);
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/* MCFG is now active. If it's not qemu was started for machine PC */
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if (CONFIG(BOOTBLOCK_CONSOLE))
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if (CONFIG(BOOTBLOCK_CONSOLE) &&
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mainboard_machine_check();
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(pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO) !=
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(CONFIG_MMCONF_BASE_ADDRESS | 1)))
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die("You must run qemu for machine Q35 (-M q35)");
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}
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}
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static void bootblock_southbridge_init(void)
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static void bootblock_southbridge_init(void)
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@ -41,9 +41,7 @@ static void qemu_nb_read_resources(struct device *dev)
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{
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{
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pci_dev_read_resources(dev);
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pci_dev_read_resources(dev);
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/* reserve mmconfig */
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mmconf_resource(dev, 2);
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fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10,
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IORESOURCE_RESERVE);
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if (CONFIG(ARCH_RAMSTAGE_X86_64)) {
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if (CONFIG(ARCH_RAMSTAGE_X86_64)) {
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/* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */
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/* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */
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@ -2,6 +2,7 @@
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#define __SIMPLE_DEVICE__
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#define __SIMPLE_DEVICE__
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#include <assert.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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@ -10,6 +11,28 @@
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#include "q35.h"
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#include "q35.h"
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static uint32_t encode_pciexbar_length(void)
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{
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switch (CONFIG_MMCONF_BUS_NUMBER) {
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case 256: return 0 << 1;
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case 128: return 1 << 1;
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case 64: return 2 << 1;
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default: return dead_code_t(uint32_t);
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}
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}
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uint32_t make_pciexbar(void)
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{
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return CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
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}
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/* Check that MCFG is active. If it's not, QEMU was started for machine PC */
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void mainboard_machine_check(void)
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{
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if (pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO) != make_pciexbar())
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die("You must run qemu for machine Q35 (-M q35)");
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}
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/* QEMU-specific register */
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/* QEMU-specific register */
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#define EXT_TSEG_MBYTES 0x50
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#define EXT_TSEG_MBYTES 0x50
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@ -4,6 +4,7 @@
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#define __MAINBOARD_EMU_Q35_H__
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#define __MAINBOARD_EMU_Q35_H__
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#include <device/pci_type.h>
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#include <device/pci_type.h>
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#include <types.h>
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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@ -23,4 +24,8 @@
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#define TSEG_SZ_MASK (3 << 1)
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#define TSEG_SZ_MASK (3 << 1)
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#define H_SMRAME (1 << 7)
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#define H_SMRAME (1 << 7)
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uint32_t make_pciexbar(void);
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void mainboard_machine_check(void);
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#endif
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#endif
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@ -8,20 +8,12 @@
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#include "q35.h"
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#include "q35.h"
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static void mainboard_machine_check(void)
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{
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/* Check that MCFG is active. If it's not qemu was started for machine PC */
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if (!CONFIG(BOOTBLOCK_CONSOLE) &&
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(pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO) !=
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(CONFIG_MMCONF_BASE_ADDRESS | 1)))
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die("You must run qemu for machine Q35 (-M q35)");
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}
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void mainboard_romstage_entry(void)
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void mainboard_romstage_entry(void)
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{
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{
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i82801ix_early_init();
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i82801ix_early_init();
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mainboard_machine_check();
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if (!CONFIG(BOOTBLOCK_CONSOLE))
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mainboard_machine_check();
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cbmem_recovery(0);
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cbmem_recovery(0);
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}
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}
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