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amd/stoneyridge: Add definitions for various NB registers

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Add #define values for the first MMIO base/limit, the first I/O
base/limit, and VGA enable registers.

Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson 2017-10-27 17:00:21 -06:00
parent 14ef26b07b
commit cbb78cd752
1 changed files with 11 additions and 0 deletions
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11
src/soc/amd/stoneyridge/include/soc/northbridge.h
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@ -26,9 +26,20 @@
# define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ # define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */
/* D18F1 - Address Map Registers */ /* D18F1 - Address Map Registers */
#define D18F1_MMIO_BASE0_LO 0x80
# define MMIO_WE (1 << 1)
# define MMIO_RE (1 << 0)
#define D18F1_MMIO_LIMIT0_LO 0x84
# define MMIO_NP (1 << 7)
#define D18F1_IO_BASE0 0xc0
# define IO_WE (1 << 1)
# define IO_RE (1 << 0)
#define D18F1_IO_LIMIT0 0xc4
#define D18F1_DRAM_HOLE 0xf0 #define D18F1_DRAM_HOLE 0xf0
# define DRAM_HOIST_VALID (1 << 1) # define DRAM_HOIST_VALID (1 << 1)
# define DRAM_HOLE_VALID (1 << 0) # define DRAM_HOLE_VALID (1 << 0)
#define D18F1_VGAEN 0xf4
# define VGA_ADDR_ENABLE (1 << 0)
enum { enum {
/* SMM handler area. */ /* SMM handler area. */