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mb/google/rex: Enable SaGv

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This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be
able to train memory (DIMM) at different frequencies.

On all latest Intel based platforms SaGv is expected to be enabled
to support dynamic switching of memory operating frequency.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7cf52b966c1355c1f2bd4ae7c256fa4252a90666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This commit is contained in:
Subrata Banik
2023-01-20 22:04:06 +05:30
parent 289f9a5566
commit cbca81c594
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
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@@ -20,6 +20,8 @@ chip soc/intel/meteorlake
# Enable CNVi BT # Enable CNVi BT
register "cnvi_bt_core" = "true" register "cnvi_bt_core" = "true"
register "sagv" = "SAGV_ENABLED"
register "serial_io_uart_mode" = "{ register "serial_io_uart_mode" = "{
[PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART1] = PchSerialIoDisabled,