diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index 3ea8f36ea8..c5f43ef22e 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -130,13 +130,6 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
 	 */
 	config->regs[CPPC_HIGHEST_PERF] = msr;
 
-	/*
-	 * Nominal Performance -> Guaranteed Performance:
-	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)},
-	 */
-	msr.bit_offset = 8;
-	config->regs[CPPC_NOMINAL_PERF] = msr;
-
 	/*
 	 * Lowest Nonlinear Performance -> Most Efficient Performance:
 	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)},
@@ -158,6 +151,15 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
 	msr.bit_offset = 8;
 	config->regs[CPPC_GUARANTEED_PERF] = msr;
 
+	msr.addrl = MSR_PLATFORM_INFO;
+
+	/*
+	 * Nominal Performance -> Maximum Non-Turbo Ratio:
+	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)},
+	 */
+	msr.bit_offset = 8;
+	config->regs[CPPC_NOMINAL_PERF] = msr;
+
 	msr.addrl = IA32_HWP_REQUEST;
 
 	/*
diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h
index a2165f365a..da0f0bb68d 100644
--- a/src/include/cpu/intel/msr.h
+++ b/src/include/cpu/intel/msr.h
@@ -12,4 +12,6 @@
 #define MSR_PIC_MSG_CONTROL	0x2e
 #define  TPR_UPDATES_DISABLE	(1 << 10)
 
+#define MSR_PLATFORM_INFO	0xce
+
 #endif /* CPU_INTEL_MSR_H */