src/cpu: Add required space before opening parenthesis '('

Change-Id: I7fb9bfcaeec0b9dfd0695d2b2d398fd01091f6bc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16286
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker

src/cpu/amd/dualcore/amd_sibling.c

@@ -37,11 +37,11 @@ static int get_max_siblings(int nodes)
 	int siblings=0;
 
 	//get max siblings from all the nodes
-	for(nodeid=0; nodeid<nodes; nodeid++){
+	for (nodeid=0; nodeid<nodes; nodeid++){
 		int j;
 		dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
 		j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
-		if(siblings < j) {
+		if (siblings < j) {
 			siblings = j;
 		}
 	}
@@ -55,7 +55,7 @@ static void enable_apic_ext_id(int nodes)
         int nodeid;
 
         //enable APIC_EXIT_ID all the nodes
-        for(nodeid=0; nodeid<nodes; nodeid++){
+        for (nodeid=0; nodeid<nodes; nodeid++){
                 uint32_t val;
                 dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
                 val = pci_read_config32(dev, 0x68);
@@ -84,7 +84,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
 	if (bsp_apic_id > 0) { // IOAPIC could start from 0
 		return 0;
-	} else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) )  { // enabled ext id but bsp = 0
+	} else if (pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) )  { // enabled ext id but bsp = 0
 		return 1;
 	}
 
@@ -92,11 +92,11 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
 #if 0
 	//it is for all e0 single core and nc_cfg_54 low is set, but in the romstage.c stage we do not set that bit for it.
-	if(nb_cfg_54 && (!disable_siblings) && (siblings == 0)) {
+	if (nb_cfg_54 && (!disable_siblings) && (siblings == 0)) {
 		//we need to check if e0 single core is there
 		int i;
-		for(i=0; i<nodes; i++) {
-			if(is_e0_later_in_bsp(i)) {
+		for (i=0; i<nodes; i++) {
+			if (is_e0_later_in_bsp(i)) {
 				siblings = 1;
 				break;
 			}
@@ -106,7 +106,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
 	//Construct apicid_base
 
-	if((!disable_siblings) && (siblings>0) ) {
+	if ((!disable_siblings) && (siblings>0) ) {
 		/* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel
 		and the kernel will try to get one that is small than 16 to make IOAPIC work.
 		I don't know when the kernel can support 256 APIC id. (APIC_EXT_ID is enabled) */
@@ -120,7 +120,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
 		apicid_base = nodes;
 	}
 
-	if((apicid_base+ioapic_num-1)>0xf) {
+	if ((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
 		printk(BIOS_INFO, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for IOAPIC\n");
 		enable_apic_ext_id(nodes);

src/cpu/amd/dualcore/dualcore.c

@@ -18,7 +18,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid)
 static inline uint8_t set_apicid_cpuid_lo(void)
 {
 #if !CONFIG_K8_REV_F_SUPPORT
-        if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set
+        if (is_cpu_pre_e0()) return 0; // pre_e0 can not be set
 #endif
 
         // set the NB_CFG[54]=1; why the OS will be happy with that ???
@@ -55,8 +55,8 @@ static inline void start_other_cores(void)
 
         nodes = get_nodes();
 
-        for(nodeid=0; nodeid<nodes; nodeid++) {
-		if( get_core_num_in_bsp(nodeid) > 0) {
+        for (nodeid=0; nodeid<nodes; nodeid++) {
+		if ( get_core_num_in_bsp(nodeid) > 0) {
 			real_start_other_core(nodeid);
 		}
 	}

src/cpu/amd/dualcore/dualcore_id.c

@@ -26,7 +26,7 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54)
 {
 	struct node_core_id id;
 	//    get the apicid via cpuid(1) ebx[27:24]
-	if( nb_cfg_54) {
+	if ( nb_cfg_54) {
                 //   when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]
                 id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
                 id.nodeid = (id.coreid>>CORE_ID_BIT);

src/cpu/amd/family_10h-family_15h/processor_name.c

@@ -331,7 +331,7 @@ int init_processor_name(void)
 		processor_name_string = unknown2;
 
 		/* String 2 */
-		for(i = 0; str2[i].value; i++) {
+		for (i = 0; str2[i].value; i++) {
 			if ((str2[i].Pg == Pg) &&
 			((str2[i].NC == NC) || !str2_checkNC) &&
 			(str2[i].String == String2)) {

src/cpu/amd/microcode/microcode.c

@@ -23,7 +23,7 @@
 #include <smp/spinlock.h>
 
 #define UCODE_DEBUG(fmt, args...)	\
-	do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while(0)
+	do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while (0)
 
 #define UCODE_MAGIC			0x00414d44
 #define UCODE_EQUIV_CPU_TABLE_TYPE	0x00000000

src/cpu/amd/model_fxx/powernow_acpi.c

@@ -775,7 +775,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 
 	/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
 	cpuid1 = cpuid(0x80000007);
-	if((cpuid1.edx & 0x6)!=0x6) {
+	if ((cpuid1.edx & 0x6)!=0x6) {
 		printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n");
 		return;
 	}
@@ -845,7 +845,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	Pstate_vid[0] = Max_vid;
 	Pstate_power[0] = data->pwr * 100;
 
-	for(Pstate_num = 1;
+	for (Pstate_num = 1;
 	    (Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0);
 	    Pstate_num++) {
 		Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f;
@@ -862,7 +862,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 
 	/* Loop over all CPU's */
 	for (dev = 0x18; dev < 0x1c; dev++) {
-		if(dev_find_slot(0, PCI_DEVFN(dev, 0)) == NULL)
+		if (dev_find_slot(0, PCI_DEVFN(dev, 0)) == NULL)
 			continue;
 
 		for (i = 0; i < (cmp_cap + 1); i++) {

src/cpu/amd/model_fxx/processor_name.c

@@ -118,10 +118,10 @@ int init_processor_name(void)
 	EightBitBrandId = cpuid_ebx(0x00000001) & 0xff;
 	BrandId = cpuid_ebx(0x80000001) & 0xffff;
 
-	if(!EightBitBrandId && !BrandId) {
+	if (!EightBitBrandId && !BrandId) {
 		BrandTableIndex = 0;
 		NN = 0xffffff;
-	} else if(!EightBitBrandId) {
+	} else if (!EightBitBrandId) {
 		BrandTableIndex = (BrandId >> 6) & 0x3f; // BrandId[11:6]
 		NN = BrandId & 0x3f; // // BrandId[6:0]
 	} else {
@@ -392,7 +392,7 @@ int init_processor_name(void)
 	 */
 
 	for (i=0; i<47; i++) { // 48 -1
-		if(program_string[i] == program_string[i+1]) {
+		if (program_string[i] == program_string[i+1]) {
 			switch (program_string[i]) {
 #if !CONFIG_K8_REV_F_SUPPORT
 			case 'X': ModelNumber = 22+ NN; break;
@@ -412,7 +412,7 @@ int init_processor_name(void)
 #endif
 			}
 
-			if(ModelNumber && ModelNumber < 100) {
+			if (ModelNumber && ModelNumber < 100) {
 				// No idea what to do with RR=100. According
 				// to the revision guide this is possible.
 				//

src/cpu/amd/mtrr/amd_mtrr.c

@@ -88,7 +88,7 @@ void amd_setup_mtrrs(void)
 		 (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0
 		((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F
 		 (((cpu_id>>16)&0xf) >= 0x4));  // Rev>=F deduced from rev tables
-	if(has_tom2wb)
+	if (has_tom2wb)
 		printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n");
 
 	/* Enable the access to AMD RdDram and WrDram extension bits */
@@ -109,7 +109,7 @@ void amd_setup_mtrrs(void)
 	sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB);
 	if (bsp_topmem2() > (uint64_t)1<<32) {
 		sys_cfg.lo |= SYSCFG_MSR_TOM2En;
-		if(has_tom2wb)
+		if (has_tom2wb)
 			sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
 	}
 
@@ -117,7 +117,7 @@ void amd_setup_mtrrs(void)
 	 * undefined side effects.
 	 */
 	msr.lo = msr.hi = 0;
-	for(i = IORR_FIRST; i <= IORR_LAST; i++) {
+	for (i = IORR_FIRST; i <= IORR_LAST; i++) {
 		wrmsr(i, msr);
 	}
 

src/cpu/amd/quadcore/amd_sibling.c

@@ -41,11 +41,11 @@ static u32 get_max_siblings(u32 nodes)
 	u32 siblings=0;
 
 	//get max siblings from all the nodes
-	for(nodeid=0; nodeid<nodes; nodeid++){
+	for (nodeid=0; nodeid<nodes; nodeid++){
 		int j;
 		dev = get_node_pci(nodeid, 3);
 		j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
-		if(siblings < j) {
+		if (siblings < j) {
 			siblings = j;
 		}
 	}
@@ -60,7 +60,7 @@ static void enable_apic_ext_id(u32 nodes)
 	u32 nodeid;
 
 	//enable APIC_EXIT_ID all the nodes
-	for(nodeid=0; nodeid<nodes; nodeid++){
+	for (nodeid=0; nodeid<nodes; nodeid++){
 		u32 val;
 		dev = get_node_pci(nodeid, 0);
 		val = pci_read_config32(dev, 0x68);
@@ -82,7 +82,7 @@ u32 get_apicid_base(u32 ioapic_num)
 
 	siblings = get_max_siblings(sysconf.nodes);
 
-	if(sysconf.bsp_apicid > 0) { // IOAPIC could start from 0
+	if (sysconf.bsp_apicid > 0) { // IOAPIC could start from 0
 		return 0;
 	} else if (sysconf.enabled_apic_ext_id)	{ // enabled ext id but bsp = 0
 		return 1;
@@ -93,7 +93,7 @@ u32 get_apicid_base(u32 ioapic_num)
 
 	//Construct apicid_base
 
-	if((!disable_siblings) && (siblings>0) ) {
+	if ((!disable_siblings) && (siblings>0) ) {
 		/* for 8 way dual core, we will used up apicid 16:16, actually
 		   16 is not allowed by current kernel and the kernel will try
 		   to get one that is small than 16 to make IOAPIC work. I don't
@@ -108,7 +108,7 @@ u32 get_apicid_base(u32 ioapic_num)
 		apicid_base = sysconf.nodes;
 	}
 
-	if((apicid_base+ioapic_num-1)>0xf) {
+	if ((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
 		printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
 		enable_apic_ext_id(sysconf.nodes);

src/cpu/amd/quadcore/quadcore_id.c

@@ -75,7 +75,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
 	 * The apicid format varies based on processor revision
 	 */
 	apicid = (cpuid_ebx(1) >> 24) & 0xff;
-	if( nb_cfg_54) {
+	if ( nb_cfg_54) {
 		if (fam15h && dual_node) {
 			id.coreid = apicid & 0x1f;
 			id.nodeid = (apicid & 0x60) >> 5;