mainboard/amenia: Enable Chrome EC Interface/Keyboard

Enabled LPC channel between host and EC.
Superio.asl will enable proper probing of onboard keyboard.

Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/14468
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/intel/amenia/Kconfig

@@ -5,6 +5,9 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_APOLLOLAKE
 	select BOARD_ROMSIZE_KB_8192
 	select MAINBOARD_HAS_CHROMEOS
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_LPC
+	select EC_GOOGLE_CHROMEEC_PD
 	select HAVE_ACPI_TABLES
 	select MAINBOARD_HAS_LPC_TPM
 	select HAVE_ACPI_RESUME

src/mainboard/intel/amenia/Makefile.inc

@@ -1,5 +1,6 @@
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 ramstage-y += mainboard.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c

src/mainboard/intel/amenia/acpi/superio.asl

@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+#define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>

src/mainboard/intel/amenia/devicetree.cb

@@ -7,6 +7,15 @@ chip soc/intel/apollolake
 	register "pcie_rp0_clkreq_pin" = "3"    # wifi/bt
 	register "pcie_rp2_clkreq_pin" = "0"    # SSD
 
+	# EC host command range is in 0x800-0x9ff
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x00fc0901"
+	register "gen3_dec" = "0x0"
+	register "gen4_dec" = "0x0"
+
+	# EC also needs 0x200,0x204, 0x60/0x64, 0x62/0x66
+	register "lpc_dec" = "0xd00"
+
 	device domain 0 on
 		device pci 00.0 on end	# - Host Bridge
 		device pci 00.1 on end	# - DPTF

src/mainboard/intel/amenia/dsdt.asl

@@ -36,4 +36,7 @@ DefinitionBlock(
 
         /* Chipset specific sleep states */
         #include <soc/intel/apollolake/acpi/sleepstates.asl>
+
+	#include "acpi/superio.asl"
+
 }

src/mainboard/intel/amenia/ec.c

@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2015 Google Inc.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+	printk(BIOS_ERR, "mainboard: EC init\n");
+	post_code(0xf0);
+
+	if (acpi_is_wakeup_s3()) {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S3_WAKE_EVENTS);
+
+		/* Disable SMI and wake events */
+		google_chromeec_set_smi_mask(0);
+
+		/* Clear pending events */
+		while (google_chromeec_get_event() != 0)
+			;
+
+		/* Restore SCI event mask */
+		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+	} else {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S5_WAKE_EVENTS);
+	}
+
+	/* Clear wake event mask */
+	google_chromeec_set_wake_mask(0);
+	post_code(0xf1);
+}

src/mainboard/intel/amenia/ec.h

@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+#ifndef __ACPI__
+extern void mainboard_ec_init(void);
+#endif
+
+#endif

src/mainboard/intel/amenia/mainboard.c

@@ -17,6 +17,8 @@
 
 #include <device/device.h>
 #include <soc/gpio.h>
+#include <soc/pci_devs.h>
+#include "ec.h"
 
 /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */
 static const struct pad_config amenia_gpios[] = {
@@ -136,6 +138,7 @@ static const struct pad_config amenia_gpios[] = {
 static void mainboard_init(void *chip_info)
 {
 	gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios));
+	mainboard_ec_init();
 }
 
 struct chip_operations mainboard_ops = {