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sb/intel/*/smihandler.c: Correct BIOS_CNTL access width

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The BIOS_CNTL register is 8 bits wide on all affected platforms.

Change-Id: Iaf9267cf27847d54ed50e1f9ae29011d0e99cf8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51939
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-03-30 10:49:24 +02:00 committed by Patrick Georgi
parent 52e6194558
commit cc36c4c235
2 changed files with 4 additions and 4 deletions
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4
src/southbridge/intel/common/smihandler.c
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@ -374,7 +374,7 @@ static void southbridge_smi_tco(void)
if (tco_sts & (1 << 8)) { // BIOSWR if (tco_sts & (1 << 8)) { // BIOSWR
u8 bios_cntl; u8 bios_cntl;
bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); bios_cntl = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) { if (bios_cntl & 1) {
/* BWE is RW, so the SMI was caused by a /* BWE is RW, so the SMI was caused by a
@ -388,7 +388,7 @@ static void southbridge_smi_tco(void)
* box. * box.
*/ */
printk(BIOS_DEBUG, "Switching back to RO\n"); printk(BIOS_DEBUG, "Switching back to RO\n");
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xdc,
(bios_cntl & ~1)); (bios_cntl & ~1));
} /* No else for now? */ } /* No else for now? */
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */

4
src/southbridge/intel/lynxpoint/smihandler.c
View File

@ -348,7 +348,7 @@ static void southbridge_smi_tco(void)
// BIOSWR // BIOSWR
if (tco_sts & (1 << 8)) { if (tco_sts & (1 << 8)) {
u8 bios_cntl = pci_read_config16(PCH_LPC_DEV, BIOS_CNTL); u8 bios_cntl = pci_read_config8(PCH_LPC_DEV, BIOS_CNTL);
if (bios_cntl & 1) { if (bios_cntl & 1) {
/* /*
@ -362,7 +362,7 @@ static void southbridge_smi_tco(void)
* box. * box.
*/ */
printk(BIOS_DEBUG, "Switching back to RO\n"); printk(BIOS_DEBUG, "Switching back to RO\n");
pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); pci_write_config8(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1));
} /* No else for now? */ } /* No else for now? */
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
/* Handle TCO timeout */ /* Handle TCO timeout */