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ACPI implementation for i945, ICH7, Kontron 986LCD-M

Browse Source 
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2009-03-13 00:44:09 +00:00 committed by Stefan Reinauer
parent 47e42e5ebb
commit cc46e73a02
25 changed files with 2719 additions and 305 deletions
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4
src/mainboard/kontron/986lcd-m/Config.lb
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@ -82,8 +82,8 @@ if HAVE_ACPI_TABLES
object fadt.o object fadt.o
object acpi_tables.o object acpi_tables.o
makerule dsdt.c makerule dsdt.c
depends "$(MAINBOARD)/dsdt.dsl" depends "$(MAINBOARD)/dsdt.asl"
action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.dsl" action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.asl"
action "mv $(PWD)/dsdt.hex dsdt.c" action "mv $(PWD)/dsdt.hex dsdt.c"
end end
object ./dsdt.o object ./dsdt.o

51
src/mainboard/kontron/986lcd-m/acpi/cpu.asl Normal file
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@ -0,0 +1,51 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* Intel Core (2) Duo CPU node support
*
* Note: The ACPI P_BLK on the ICH7 (and probably others) lives at
* PMBASE + 0x10, and it's 0x06 bytes long. On ICH8 it's 8 bytes.
*
* The second CPU core does not need its own P_BLK.
*/
Scope(\_PR)
{
Processor(
CPU1, // name of cpu/core 0
1, // numeric id of cpu/core
0x510, // ACPI P_BLK base address
6 // ACPI P_BLK size
)
{
// TODO: _PDT
}
Processor(
CPU2, // name of cpu/core 1
2, // numeric id of cpu/core 1
0, // ACPI P_BLK base address
0) // ACPI P_BLK size
{
// TODO: _PDT
}
} // End _PR

51
src/mainboard/kontron/986lcd-m/acpi/ec.asl Normal file
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@ -0,0 +1,51 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Device(EC0)
{
Name (_HID, EISAID("PNP0C09"))
Name (_UID, 1)
Method (_CRS, 0)
{
Name (ECMD, ResourceTemplate()
{
IO (Decode16, 0x62, 0x62, 0, 1)
IO (Decode16, 0x66, 0x66, 0, 1)
})
Return (ECMD)
}
Method (_REG, 2)
{
// This method is needed by Windows XP/2000
// for EC initialization before a driver
// is loaded
}
Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
// TODO EC Query methods
// TODO Scope _SB devices for AC power, LID, Power button
}

42
src/mainboard/kontron/986lcd-m/acpi/globalnvs.asl Normal file
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@ -0,0 +1,42 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* Global Variables */
Name(\PICM,0) // IOAPIC/8259
/* Global ACPI memory region. This region is used for passing information
* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
* Since we don't know where this will end up in memory at ACPI compile time,
* we have to fix it up in coreboot's ACPI creation phase.
*/
OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xFF)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
Offset (0x00),
OSYS, 16, // 0x00 Operating System
SMIF, 8, // 0x02 SMI function
Offset (0x10),
MPEN, 8, // 0x10 Multi Processor Enable
}

93
src/mainboard/kontron/986lcd-m/acpi/platform.asl Normal file
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@ -0,0 +1,93 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2)
Field (APMP, ByteAcc, NoLock, Preserve)
{
APMC, 8, // APM command
APMS, 8 // APM status
}
/* Port 80 POST */
OperationRegion (POST, SystemIO, 0x80, 1)
Field (POST, ByteAcc, Lock, Preserve)
{
DBG0, 8
}
/* SMI I/O Trap */
Method(TRAP, 1, Serialized)
{
Store (Arg0, SMIF) // SMI Function
Store (0, TRP0) // Generate trap
Return (SMIF) // Return value of SMI handler
}
/* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/
Method(_PIC, 1)
{
// Remember the OS' IRQ routing choice.
Store(Arg0, PICM)
}
/* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
Method(_PTS,1)
{
// Call a trap so SMI can prepare for Sleep as well.
// TRAP(0x55)
}
/* The _WAK method is called on system wakeup */
Method(_WAK,1)
{
// CPU specific part
// Notify PCI Express slots in case a card
// was inserted while a sleep state was active.
// Are we going to S3?
If (LEqual(Arg0, 3)) {
// ..
}
// Are we going to S4?
If (LEqual(Arg0, 4)) {
// ..
}
// TODO: Windows XP SP2 P-State restore
Return(Package(){0,0})
}

27
src/mainboard/kontron/986lcd-m/acpi/sleepstates.asl Normal file
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@ -0,0 +1,27 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Name(\_S0, Package(4){0x0,0x0,0,0})
Name(\_S1, Package(4){0x1,0x0,0,0})
Name(\_S3, Package(4){0x5,0x0,0,0})
Name(\_S4, Package(4){0x6,0x0,0,0})
Name(\_S5, Package(4){0x7,0x0,0,0})

48
src/mainboard/kontron/986lcd-m/acpi/superio.asl Normal file
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@ -0,0 +1,48 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Device (SIO1)
{
Name (_HID, EISAID("PNP0A05"))
Name (_UID, 1)
Device (UAR1)
{
Name(_HID, EISAID("PNP0501"))
Name(_UID, 1)
// Some methods need an implementation here:
// missing: _STA, _DIS, _CRS, _PRS,
// missing: _SRS, _PS0, _PS3
}
Device (UAR2)
{
Name(_HID, EISAID("PNP0501"))
Name(_UID, 2)
// Some methods need an implementation here:
// missing: _STA, _DIS, _CRS, _PRS,
// missing: _SRS, _PS0, _PS3
}
}

96
src/mainboard/kontron/986lcd-m/acpi/thermal.asl Normal file
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@ -0,0 +1,96 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
// Thermal Zone
Scope (\_TZ)
{
ThermalZone (THRM)
{
// FIXME these could/should be read from the
// GNVS area, so they can be controlled by
// coreboot
Name(TC1V, 0x04)
Name(TC2V, 0x03)
Name(TSPV, 0x64)
// At which temperature should the OS start
// active cooling?
Method (_AC0, 0, Serialized)
{
Return (0xf5c) // Value for Rocky
}
// Method (_AC1, 0, Serialized)
// {
// Return (0xf5c)
// }
// Critical shutdown temperature
Method (_CRT, 0, Serialized)
{
Return (Add (0x0aac, 0x50)) // FIXME
}
// CPU throttling start temperature
Method (_PSV, 0, Serialized)
{
Return (0xaaf) // FIXME
}
// Get DTS Temperature
Method (_TMP, 0, Serialized)
{
Return (0xaac) // FIXME
}
// Processors used for active cooling
Method (_PSL, 0, Serialized)
{
If (MPEN) {
Return (Package() {\_PR.CPU1, \_PR.CPU2})
}
Return (Package() {\_PR.CPU1})
}
// TC1 value for passive cooling
Method (_TC1, 0, Serialized)
{
Return (TC1V)
}
// TC2 value for passive cooling
Method (_TC2, 0, Serialized)
{
Return (TC2V)
}
// Sampling period for passive cooling
Method (_TSP, 0, Serialized)
{
Return (TSPV)
}
}
}

45
src/mainboard/kontron/986lcd-m/acpi/video.asl Normal file
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@ -0,0 +1,45 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
// Brightness write
Method (BRTW, 1, Serialized)
{
// TODO
}
// Hot Key Display Switch
Method (HKDS, 1, Serialized)
{
// TODO
}
// Lid Switch Display Switch
Method (LSDS, 1, Serialized)
{
// TODO
}
// Brightness Notification
Method(BRTN,1,Serialized)
{
// TODO (no displays defined yet)
}

55
src/mainboard/kontron/986lcd-m/dsdt.asl Normal file
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@ -0,0 +1,55 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv2", // OEM id
"COREBOOT", // OEM table id
0x00000001 // OEM revision
)
{
// Some generic macros
Include ("acpi/platform.asl")
// global NVS and variables
Include ("acpi/globalnvs.asl")
// General Purpose Events
//include ("acpi/gpe.asl")
/* CPU node(s) */
include ("acpi/cpu.asl")
//include ("acpi/thermal.asl")
Scope (\_SB) {
Device (PCI0)
{
Include ("../../../northbridge/intel/i945/acpi/i945.asl")
include ("../../../southbridge/intel/i82801gx/acpi/ich7.asl")
}
}
/* Board and Chipset specific sleep states */
include ("acpi/sleepstates.asl")
}

303
src/mainboard/kontron/986lcd-m/dsdt.dsl
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@ -1,303 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
DefinitionBlock ("DSDT", "DSDT", 1, "986LCD", "COREBOOT", 0x0000001)
{
Scope (\_PR)
{
Processor (CPU1, 0x01, 0x00000810, 0x06)
{
OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
Name (NCPU, 0x80)
Name (TYPE, 0x80000000)
Name (HNDL, 0x80000000)
Name (CFGD, 0x80000000)
Name (TBLD, 0x80)
Method (_PDC, 1, NotSerialized)
{
}
}
}
Scope (\_PR)
{
Processor (CPU2, 0x02, 0x00000000, 0x00)
{
OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
Name (NCPU, 0x80)
Name (TYPE, 0x80000000)
Name (HNDL, 0x80000000)
Name (CFGD, 0x80000000)
Name (TBLD, 0x80)
Method (_PDC, 1, NotSerialized)
{
}
}
}
Name (PICM, 0x00)
Method (_PIC, 1, NotSerialized)
{
Store (Arg0, PICM)
}
Scope (\_SB)
{
Name (PR00, Package (0x12)
{
Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 },
Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 },
Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 },
Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 },
Package (0x04) { 0x001FFFFF, 0x00, LNKC, 0x00 },
Package (0x04) { 0x001FFFFF, 0x01, LNKD, 0x00 },
Package (0x04) { 0x001DFFFF, 0x00, LNKH, 0x00 },
Package (0x04) { 0x001DFFFF, 0x01, LNKD, 0x00 },
Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 },
Package (0x04) { 0x001DFFFF, 0x03, LNKA, 0x00 },
Package (0x04) { 0x001EFFFF, 0x00, LNKB, 0x00 },
Package (0x04) { 0x001EFFFF, 0x01, LNKE, 0x00 },
Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 },
Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 },
Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 },
Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 },
Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 },
Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }
})
Name (AR00, Package (0x12)
{
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x12 },
Package (0x04) { 0x001FFFFF, 0x01, 0x00, 0x13 },
Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x17 },
Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x13 },
Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x10 },
Package (0x04) { 0x001EFFFF, 0x00, 0x00, 0x11 },
Package (0x04) { 0x001EFFFF, 0x01, 0x00, 0x14 },
Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 },
Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 },
Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x10 }
})
Name (PR01, Package (0x1D)
{
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
Package (0x04) { 0x0001FFFF, 0x00, LNKE, 0x00 },
Package (0x04) { 0x0001FFFF, 0x01, LNKF, 0x00 },
Package (0x04) { 0x0001FFFF, 0x02, LNKG, 0x00 },
Package (0x04) { 0x0001FFFF, 0x03, LNKH, 0x00 },
Package (0x04) { 0x0002FFFF, 0x00, LNKF, 0x00 },
Package (0x04) { 0x0002FFFF, 0x01, LNKG, 0x00 },
Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 },
Package (0x04) { 0x0002FFFF, 0x03, LNKE, 0x00 },
Package (0x04) { 0x0003FFFF, 0x00, LNKG, 0x00 },
Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 },
Package (0x04) { 0x0003FFFF, 0x02, LNKE, 0x00 },
Package (0x04) { 0x0003FFFF, 0x03, LNKF, 0x00 },
Package (0x04) { 0x0004FFFF, 0x00, LNKH, 0x00 },
Package (0x04) { 0x0004FFFF, 0x01, LNKE, 0x00 },
Package (0x04) { 0x0004FFFF, 0x02, LNKF, 0x00 },
Package (0x04) { 0x0004FFFF, 0x03, LNKG, 0x00 },
Package (0x04) { 0x0005FFFF, 0x00, LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x01, LNKC, 0x00 },
Package (0x04) { 0x0005FFFF, 0x02, LNKB, 0x00 },
Package (0x04) { 0x0005FFFF, 0x03, LNKA, 0x00 },
Package (0x04) { 0x0006FFFF, 0x00, LNKC, 0x00 },
Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 },
Package (0x04) { 0x0006FFFF, 0x02, LNKA, 0x00 },
Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 },
Package (0x04) { 0x0009FFFF, 0x00, LNKF, 0x00 },
Package (0x04) { 0x0009FFFF, 0x01, LNKG, 0x00 },
Package (0x04) { 0x0009FFFF, 0x02, LNKH, 0x00 },
Package (0x04) { 0x0009FFFF, 0x03, LNKE, 0x00 }
})
Name (AR01, Package (0x1D)
{
Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 },
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x14 },
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 },
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x16 },
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 },
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 },
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 },
Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x17 },
Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x14 },
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x16 },
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x17 },
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x14 },
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x15 },
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x17 },
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x14 },
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x15 },
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x16 },
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x13 },
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x11 },
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 },
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 },
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 },
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x15 },
Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x16 },
Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x17 },
Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x14 }
})
Name (PR04, Package (0x04)
{
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }
})
Name (AR04, Package (0x04)
{
Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 },
Package (0x04) { 0xFFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0xFFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0xFFFF, 0x03, 0x00, 0x13 }
})
Name (PR05, Package (0x01)
{
Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 }
})
Name (AR05, Package (0x01)
{
Package (0x04) { 0xFFFF, 0x00, 0x00, 0x11 }
})
Name (PR06, Package (0x01)
{
Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 }
})
Name (AR06, Package (0x01)
{
Package (0x04) { 0xFFFF, 0x00, 0x00, 0x12 }
})
Name (PR07, Package (0x04)
{
Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 },
Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 },
Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 },
Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 }
})
Name (AR07, Package (0x04)
{
Package (0x04) { 0xFFFF, 0x00, 0x00, 0x13 },
Package (0x04) { 0xFFFF, 0x01, 0x00, 0x10 },
Package (0x04) { 0xFFFF, 0x02, 0x00, 0x11 },
Package (0x04) { 0xFFFF, 0x03, 0x00, 0x12 }
})
Name (PR08, Package (0x04)
{
Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }
})
Name (AR08, Package (0x04)
{
Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 },
Package (0x04) { 0xFFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0xFFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0xFFFF, 0x03, 0x00, 0x13 }
})
Name (PR09, Package (0x04)
{
Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 },
Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 },
Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 },
Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 }
})
Name (AR09, Package (0x04)
{
Package (0x04) { 0xFFFF, 0x00, 0x00, 0x11 },
Package (0x04) { 0xFFFF, 0x01, 0x00, 0x12 },
Package (0x04) { 0xFFFF, 0x02, 0x00, 0x13 },
Package (0x04) { 0xFFFF, 0x03, 0x00, 0x10 }
})
Device (LNKA)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x01)
}
Device (LNKB)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x02)
}
Device (LNKC)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x03)
}
Device (LNKD)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x04)
}
Device (LNKE)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x05)
}
Device (LNKF)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x06)
}
Device (LNKG)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x07)
}
Device (LNKH)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x08)
}
}
Name (\_S0, Package (0x04)
{ 0x00, 0x00, 0x00, 0x00 })
Name (\_S1, Package (0x04)
{ 0x01, 0x00, 0x00, 0x00 })
Name (\_S3, Package (0x04)
{ 0x05, 0x00, 0x00, 0x00 })
Name (\_S4, Package (0x04)
{ 0x06, 0x00, 0x00, 0x00 })
Name (\_S5, Package (0x04)
{ 0x07, 0x00, 0x00, 0x00 })
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Include ("../../../northbridge/intel/i945/acpi/i945_hostbridge.asl")
/* PCI Device Resource Consumption */
Device (PDRC)
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
})
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
Return(PDRS)
}
}
// PCIe graphics port 0:1.0
Include ("../../../northbridge/intel/i945/acpi/i945_peg.asl")
// Integrated graphics 0:2.0
Include ("../../../northbridge/intel/i945/acpi/i945_igd.asl")
Scope (\)
{
// backlight control, display switching, lid
Include ("acpi/video.asl")
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI
Device (MCHC)
{
Name(_ADR, 0x00000000) // 0:0.0
OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
Field (MCHP, DWordAcc, NoLock, Preserve)
{
Offset (0x40), // EPBAR
EPEN, 1, // Enable
, 11, //
EPBR, 20, // EPBAR
Offset (0x48), // MCHBAR
MHEN, 1, // Enable
, 13, //
MHBR, 18, // MCHBAR
Offset (0x60), // PCIe BAR
PXEN, 1, // Enable
PXSZ, 2, // BAR size
, 23, //
PXBR, 6, // PCIe BAR
Offset (0x68), // DMIBAR
DMEN, 1, // Enable
, 11, //
DMBR, 20, // DMIBAR
// ...
Offset (0x90), // PAM0
, 4,
PM0H, 2,
, 2,
Offset (0x91), // PAM1
PM1L, 2,
, 2,
PM1H, 2,
, 2,
Offset (0x92), // PAM2
PM2L, 2,
, 2,
PM2H, 2,
, 2,
Offset (0x93), // PAM3
PM3L, 2,
, 2,
PM3H, 2,
, 2,
Offset (0x94), // PAM4
PM4L, 2,
, 2,
PM4H, 2,
, 2,
Offset (0x95), // PAM5
PM5L, 2,
, 2,
PM5H, 2,
, 2,
Offset (0x96), // PAM6
PM6L, 2,
, 2,
PM6H, 2,
, 2,
Offset (0xa2), // Top of upper used dram
TUUD, 16,
Offset (0xb0),
, 4,
TLUD, 12 // TOLUD
}
}
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
// IO Region 0
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
// PCI Config Space
Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
// IO Region 1
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
// VGA memory (0xa0000-0xbffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
0x00020000,,, ASEG)
// OPROM reserved (0xc0000-0xc3fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
0x00004000,,, OPR0)
// OPROM reserved (0xc4000-0xc7fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
0x00004000,,, OPR1)
// OPROM reserved (0xc8000-0xcbfff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
0x00004000,,, OPR2)
// OPROM reserved (0xcc000-0xcffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
0x00004000,,, OPR3)
// OPROM reserved (0xd0000-0xd3fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
0x00004000,,, OPR4)
// OPROM reserved (0xd4000-0xd7fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
0x00004000,,, OPR5)
// OPROM reserved (0xd8000-0xdbfff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
0x00004000,,, OPR6)
// OPROM reserved (0xdc000-0xdffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
0x00004000,,, OPR7)
// Bios Extension (0xe0000-0xeffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e0000, 0x000effff, 0x00000000,
0x00010000,,, ESEG)
// System BIOS (0xf0000-0xfffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
// PCI Memory Region (Top of memory-0xfebfffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
0x00000000,,, PM01)
})
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
// Fix up PCI memory region:
// Enter actual TOLUD. The TOLUD register contains bits 20-31 of
// the top of memory address.
ShiftLeft (^MCHC.TLUD, 20, PMIN)
Add(Subtract(PMAX, PMIN), 1, PLEN)
Return (MCRS)
}
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// PCIe Graphics 0:1.0
Package() { 0x0001ffff, 0, 0, 16 },
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, 0, 16 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 16 },
Package() { 0x001cffff, 1, 0, 17 },
Package() { 0x001cffff, 2, 0, 18 },
Package() { 0x001cffff, 3, 0, 19 },
// USB and EHCI 0:1d.x
Package() { 0x001dffff, 0, 0, 23 },
Package() { 0x001dffff, 1, 0, 19 },
Package() { 0x001dffff, 2, 0, 18 },
Package() { 0x001dffff, 3, 0, 16 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, 0, 19 },
Package() { 0x001fffff, 1, 0, 19},
Package() { 0x001fffff, 2, 0, 19 },
Package() { 0x001fffff, 3, 0, 16 }
})
} Else {
Return (Package() {
// PCIe Graphics 0:1.0
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
// USB and EHCI 0:1d.x
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
})
}
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Device (GFX0)
{
Name (_ADR, 0x00020000)
// TODO display switching etc
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Device (PEGP)
{
Name (_ADR, 0x00010000)
// PCI Interrupt Routing.
Method (_PRT)
{
If (PICM) {
Return (Package() {
Package() { 0x0000ffff, 0, 0, 16 },
Package() { 0x0000ffff, 1, 0, 17 },
Package() { 0x0000ffff, 2, 0, 18 },
Package() { 0x0000ffff, 3, 0, 19 }
})
} Else {
Return (Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
})
}
}
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* Intel i82801G support
*/
Scope(\)
{
// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
OperationRegion(IO_T, SystemIO, 0x800, 0x10)
Field(IO_T, ByteAcc, NoLock, Preserve)
{
Offset(0x8),
TRP0, 8 // IO-Trap at 0x808
}
// ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
// this doesn't work as ACPI initializes regions and packages first, devices second.
// use dynamic operation region? if so, how? XXX
//OperationRegion(PMIO, SystemIO, And(\_SB_.PCI0.LPCB.PMBS, 0xfffc), 0x80)
OperationRegion(PMIO, SystemIO, 0x500, 0x80)
Field(PMIO, ByteAcc, NoLock, Preserve)
{
Offset(0x42), // General Purpose Control
, 1, // skip 1 bit
GPEC, 1, // TCO status
, 9, // skip 9 more bits
SCIS, 1, // TCO DMI status
, 6 // To the end of the word
}
// ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
OperationRegion(GPIO, SystemIO, 0x1180, 0x3c)
Field(GPIO, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // GPIO Use Select
GU00, 8,
GU01, 8,
GU02, 8,
GU03, 8,
Offset(0x04), // GPIO IO Select
GIO0, 8,
GIO1, 8,
GIO2, 8,
GIO3, 8,
Offset(0x0c), // GPIO Level
GL00, 8,
GL01, 8,
, 3,
GP27, 1, // SATA_PWR_EN #0
GP28, 1, // SATA_PWR_EN #1
, 3,
Offset(0x18), // GPIO Blink
GB00, 8,
GB01, 8,
GB02, 8,
GB03, 8,
Offset(0x2c), // GPIO Invert
GIV0, 8,
GIV1, 8,
GIV2, 8,
GIV3, 8,
Offset(0x30), // GPIO Use Select 2
GU04, 8,
GU05, 8,
GU06, 8,
GU07, 8,
Offset(0x34), // GPIO IO Select 2
GIO4, 8,
GIO5, 8,
GIO6, 8,
GIO7, 8,
Offset(0x38), // GPIO Level 2
, 5,
GP37, 1, // PATA_PWR_EN
, 2,
GL05, 8,
GL06, 8,
GL07, 8
}
// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, 0xfff1000, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve)
{
Offset(0x0000), // Backbone
Offset(0x1000), // Chipset
Offset(0x3000), // Legacy Configuration Registers
Offset(0x3404), // High Performance Timer Configuration
HPAS, 2, // Address Select
, 5,
HPTE, 1, // Address Enable
Offset(0x3418), // FD (Function Disable)
, 1,
PATD, 1, // PATA disable
SATD, 1, // SATA disable
SMBD, 1, // SMBUS disable
HDAD, 1, // Azalia disable
, 11, // ... FIXME
RP1D, 1, // Root Port 1 disable
RP2D, 1, // Root Port 2 disable
RP3D, 1, // Root Port 3 disable
RP4D, 1, // Root Port 4 disable
RP5D, 1, // Root Port 5 disable
RP6D, 1 // Root Port 6 disable
}
}
// 0:1b.0 High Definition Audio (Azalia)
Include ("../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl")
// PCI Express Ports
Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl")
// USB
Include ("../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl")
// PCI Bridge
Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl")
// LPC Bridge
Include ("../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl")
// PATA
Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl")
// SATA
Include ("../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl")
// SMBus
Include ("../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl")

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* Intel i82801G HDA */
// Intel High Definition Audio (Azalia) 0:1b.0
Device (HDEF)
{
Name (_ADR, 0x001b0000)
Name (_PRW, Package(){ 13, 4 })
}

493
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Device (LNKA)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 1)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTA)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLA, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLA, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTA
ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
Return (RTLA)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTA)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTA, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKB)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 2)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTB)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLB, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLB, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTB
ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
Return (RTLB)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTB)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTB, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKC)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 3)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTC)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLC, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLC, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTC
ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
Return (RTLC)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTC)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTC, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKD)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 4)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTD)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLD, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLD, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTD
ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
Return (RTLD)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTD)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTD, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKE)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 5)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTE)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLE, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLE, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTE
ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
Return (RTLE)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTE)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTE, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKF)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 6)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTF)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLF, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLF, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTF
ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
Return (RTLF)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTF)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTF, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKG)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 7)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTG)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLG, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLG, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTG
ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
Return (RTLG)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTG)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTG, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}
Device (LNKH)
{
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 8)
// Disable method
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTH)
}
// Possible Resource Settings for this Link
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
// Current Resource Settings for this link
Method (_CRS, 0, Serialized)
{
Name (RTLH, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared) {}
})
CreateWordField(RTLH, 1, IRQ0)
// Clear the WordField
Store (Zero, IRQ0)
// Set the bit from PRTH
ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
Return (RTLH)
}
// Set Resource Setting for this IRQ link
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
// Which bit is set?
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTH)
}
// Status
Method (_STA, 0, Serialized)
{
If(And(PRTH, 0x80)) {
Return (0x9)
} Else {
Return (0xb)
}
}
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
{
Name(_ADR, 0x001f0000)
OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
Field (LPC0, AnyAcc, NoLock, Preserve)
{
Offset (0x40),
PMBS, 16, // PMBASE
Offset (0x60), // Interrupt Routing Registers
PRTA, 8,
PRTB, 8,
PRTC, 8,
PRTD, 8,
Offset (0x68),
PRTE, 8,
PRTF, 8,
PRTG, 8,
PRTH, 8,
Offset (0x80), // IO Decode Ranges
IOD0, 8,
IOD1, 8,
Offset (0xf0), // RCBA
RCEN, 1,
, 13,
RCBA, 18,
}
Include ("../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl")
Include ("acpi/ec.asl")
Device (DMAC) // DMA Controller
{
Name(_HID, EISAID("PNP0200"))
Name(_CRS, ResourceTemplate()
{
IO (Decode16, 0x00, 0x00, 0x01, 0x20)
IO (Decode16, 0x81, 0x81, 0x01, 0x11)
IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
})
}
Device (FWHD) // Firmware Hub
{
Name (_HID, EISAID("INT0800"))
Name (_CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
})
}
Device (HPET)
{
Name (_HID, EISAID("PNP0103"))
Name (_CID, EISAID("PNP0C01"))
Name(BUF0, ResourceTemplate()
{
Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0)
})
Method (_STA, 0) // Device Status
{
If (HPTE) {
// Note: Ancient versions of Windows don't want
// to see the HPET in order to work right
// Return (0xb) // Enable and don't show device
Return (0xf) // Enable and show device
}
Return (0x0) // Not enabled, don't show.
}
Method (_CRS, 0, Serialized)
{
// Here we could do crazy stuff like move the HPET. Why
// should we?
Return (BUF0)
}
}
Device(PIC) // 8259 Interrupt Controller
{
Name(_HID,EISAID("PNP0000"))
Name(_CRS, ResourceTemplate()
{
IO (Decode16, 0x20, 0x20, 0x01, 0x02)
IO (Decode16, 0x24, 0x24, 0x01, 0x02)
IO (Decode16, 0x28, 0x28, 0x01, 0x02)
IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
IO (Decode16, 0x30, 0x30, 0x01, 0x02)
IO (Decode16, 0x34, 0x34, 0x01, 0x02)
IO (Decode16, 0x38, 0x38, 0x01, 0x02)
IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
IO (Decode16, 0xac, 0xac, 0x01, 0x02)
IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
IO (Decode16, 0x4d0, 0x4b0, 0x01, 0x02)
IRQNoFlags () { 2 }
})
}
Device(MATH) // FPU
{
Name (_HID, EISAID("PNP0C04"))
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
IRQNoFlags() { 13 }
})
}
Device(MISC) // Various other devices
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 2)
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
IO (Decode16, 0x61, 0x61, 0x1, 0x1) // NMI Status
IO (Decode16, 0x63, 0x63, 0x1, 0x1) // CPU Reserved
IO (Decode16, 0x65, 0x65, 0x1, 0x1) // CPU Reserved
IO (Decode16, 0x67, 0x67, 0x1, 0x1) // CPU Reserved
IO (Decode16, 0x80, 0x80, 0x1, 0x1) // Port 80 Post
IO (Decode16, 0x92, 0x92, 0x1, 0x1) // CPU Reserved
IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
IO (Decode16, 0x680, 0x680, 0x1, 0x70) // IO ???
IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap
IO (Decode16, 0x0500, 0x0500, 0x1, 0x80) // ICH7-M ACPI
IO (Decode16, 0x1180, 0x1180, 0x1, 0x40) // ICH7-M GPIO
IO (Decode16, 0x1640, 0x1640, 0x1, 0x10) // IO ???
})
}
Device (RTC) // Real Time Clock
{
Name (_HID, EISAID("PNP0B00"))
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x70, 0x70, 1, 8)
IRQNoFlags() { 8 }
})
}
Device (TIMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
{
IO (Decode16, 0x40, 0x40, 0x01, 0x04)
IO (Decode16, 0x50, 0x50, 0x10, 0x04)
IRQNoFlags() {0}
})
}
Include ("acpi/superio.asl")
Device (PS2K) // Keyboard
{
Name(_HID, EISAID("PNP0303"))
Name(_CRS, ResourceTemplate()
{
IO (Decode16, 0x60, 0x60, 0x01, 0x01)
IO (Decode16, 0x64, 0x64, 0x01, 0x01)
IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1
})
}
Device (PS2M) // Mouse
{
Name(_HID, EISAID("PNP0F13"))
Name(_CRS, ResourceTemplate()
{
IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12
})
}
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
// Intel PATA Controller 0:1f.1
Device (PATA)
{
Name (_ADR, 0x001f0001)
Device (PRID)
{
Name (_ADR, 0)
// Get Timing Mode
Method (_GTM)
{
Name(PBUF, Buffer(20) {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00 })
CreateDwordField (PBUF, 0, PIO0)
CreateDwordField (PBUF, 4, DMA0)
CreateDwordField (PBUF, 8, PIO1)
CreateDwordField (PBUF, 12, DMA1)
CreateDwordField (PBUF, 16, FLAG)
// TODO fill return structure
Return (PBUF)
}
// Set Timing Mode
Method (_STM, 3)
{
CreateDwordField (Arg0, 0, PIO0)
CreateDwordField (Arg0, 4, DMA0)
CreateDwordField (Arg0, 8, PIO1)
CreateDwordField (Arg0, 12, DMA1)
CreateDwordField (Arg0, 16, FLAG)
// TODO: Do the deed
}
Device (DSK0)
{
Name (_ADR, 0)
// TODO: _RMV ?
// TODO: _GTF ?
}
Device (DSK1)
{
Name (_ADR, 1)
// TODO: _RMV ?
// TODO: _GTF ?
}
}
}

99
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
// Intel PCI to PCI bridge 0:1e.0
Device (PCIB)
{
Name (_ADR, 0x001e0000)
Device (SLT1)
{
Name (_ADR, 0x00000000)
Name (_PRW, Package(){ 11, 4 })
}
Device (SLT2)
{
Name (_ADR, 0x00010000)
Name (_PRW, Package(){ 11, 4 })
}
Device (SLT3)
{
Name (_ADR, 0x00020000)
Name (_PRW, Package(){ 11, 4 })
}
// TODO: How many slots, where?
// PCI Interrupt Routing.
// If PICM is set, interrupts are routed over the i8259, otherwise
// over the IOAPIC. (Really? If they're above 15 they need to be routed
// fixed over the IOAPIC?)
Method (_PRT)
{
If (PICM) {
Return (Package() {
// PCI Slot 1 routes FGHE
Package() { 0x0000ffff, 0, 0, 16}, /* Firewire */
Package() { 0x0000ffff, 1, 0, 22},
Package() { 0x0000ffff, 2, 0, 23},
Package() { 0x0000ffff, 3, 0, 20},
// PCI Slot 2 routes GFEH (but is EFGH now, because that actually works)
Package() { 0x0001ffff, 0, 0, 20},
Package() { 0x0001ffff, 1, 0, 21},
Package() { 0x0001ffff, 2, 0, 22},
Package() { 0x0001ffff, 3, 0, 23},
// PCI Slot 3 routes CDBA
Package() { 0x0002ffff, 0, 0, 18},
Package() { 0x0002ffff, 1, 0, 19},
Package() { 0x0002ffff, 2, 0, 17},
Package() { 0x0002ffff, 3, 0, 16}
})
} Else {
Return (Package() {
// PCI Slot 1 routes FGHE
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
// PCI Slot 2 routes GFEH
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
// PCI Slot 3 routes CDBA
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
})
}
}
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* Intel i82801G PCIe support */
// PCI Express Ports
Device (RP01)
{
NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation?
//Include ("pcie_port.asl")
Method(_PRT)
{
If (PICM) {
Return (Package() {
Package() { 0x0000ffff, 0, 0, 16 },
Package() { 0x0000ffff, 1, 0, 17 },
Package() { 0x0000ffff, 2, 0, 18 },
Package() { 0x0000ffff, 3, 0, 19 }
})
} Else {
Return (Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
})
}
}
}
Device (RP02)
{
NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation?
//Include ("pcie_port.asl")
Method(_PRT)
{
If (PICM) {
Return (Package() {
Package() { 0x0000ffff, 0, 0, 17 },
Package() { 0x0000ffff, 1, 0, 18 },
Package() { 0x0000ffff, 2, 0, 19 },
Package() { 0x0000ffff, 3, 0, 16 }
})
} Else {
Return (Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
})
}
}
}
Device (RP03)
{
NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation?
//Include ("pcie_port.asl")
Method(_PRT)
{
If (PICM) {
Return (Package() {
Package() { 0x0000ffff, 0, 0, 18 },
Package() { 0x0000ffff, 1, 0, 19 },
Package() { 0x0000ffff, 2, 0, 16 },
Package() { 0x0000ffff, 3, 0, 17 }
})
} Else {
Return (Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }
})
}
}
}
Device (RP04)
{
NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation?
//Include ("pcie_port.asl")
Method(_PRT)
{
If (PICM) {
Return (Package() {
Package() { 0x0000ffff, 0, 0, 19 },
Package() { 0x0000ffff, 1, 0, 16 },
Package() { 0x0000ffff, 2, 0, 17 },
Package() { 0x0000ffff, 3, 0, 18 }
})
} Else {
Return (Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }
})
}
}
}
Device (RP05)
{
NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation?
//Include ("pcie_port.asl")
Method(_PRT)
{
If (PICM) {
Return (Package() {
Package() { 0x0000ffff, 0, 0, 16 },
Package() { 0x0000ffff, 1, 0, 17 },
Package() { 0x0000ffff, 2, 0, 18 },
Package() { 0x0000ffff, 3, 0, 19 }
})
} Else {
Return (Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
})
}
}
}
Device (RP06)
{
NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation?
//Include ("pcie_port.asl")
Method(_PRT)
{
If (PICM) {
Return (Package() {
Package() { 0x0000ffff, 0, 0, 17 },
Package() { 0x0000ffff, 1, 0, 18 },
Package() { 0x0000ffff, 2, 0, 19 },
Package() { 0x0000ffff, 3, 0, 16 }
})
} Else {
Return (Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
})
}
}
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
// Intel SATA Controller 0:1f.2
// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily
// pluggable
Device (SATA)
{
Name (_ADR, 0x001f0002)
Device (PRID)
{
Name (_ADR, 0)
// Get Timing Mode
Method (_GTM)
{
Name(PBUF, Buffer(20) {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00 })
CreateDwordField (PBUF, 0, PIO0)
CreateDwordField (PBUF, 4, DMA0)
CreateDwordField (PBUF, 8, PIO1)
CreateDwordField (PBUF, 12, DMA1)
CreateDwordField (PBUF, 16, FLAG)
// TODO fill return structure
Return (PBUF)
}
// Set Timing Mode
Method (_STM, 3)
{
CreateDwordField (Arg0, 0, PIO0)
CreateDwordField (Arg0, 4, DMA0)
CreateDwordField (Arg0, 8, PIO1)
CreateDwordField (Arg0, 12, DMA1)
CreateDwordField (Arg0, 16, FLAG)
// TODO: Do the deed
}
Device (DSK0)
{
Name (_ADR, 0)
// TODO: _RMV ?
// TODO: _GTF ?
}
Device (DSK1)
{
Name (_ADR, 1)
// TODO: _RMV ?
// TODO: _GTF ?
}
}
}

244
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
// Intel SMBus Controller 0:1f.3
Device (SBUS)
{
Name (_ADR, 0x001f0003)
OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
Field(SMBP, DWordAcc, NoLock, Preserve)
{
Offset(0x40),
, 2,
I2CE, 1
}
OperationRegion (SMBI, SystemIO, 0x500, 0x20)
Field (SMBI, ByteAcc, NoLock, Preserve)
{
HSTS, 8, // Host Status
, 8,
HCNT, 8, // Host Control
HCMD, 8, // Host Command
TXSA, 8, // Transmit Slave Address
DAT0, 8, // Host Data 0
DAT1, 8, // Host Data 1
HBDB, 8, // Host Block Data Byte
PECK, 8, // Packet Error Check
RXSA, 8, // Receive Slave Address
RXDA, 16, // Receive Slave Data
AUXS, 8, // Auxiliary Status
AUXC, 8, // Auxiliary Control
SLPC, 8, // SMLink Pin Control
SBPC, 8, // SMBus Pin Control
SSTS, 8, // Slave Status
SCMD, 8, // Slave Command
NADR, 8, // Notify Device Address
NDLB, 8, // Notify Data Low Byte
NDLH, 8, // Notify Data High Byte
}
// Kill all SMBus communication
Method (KILL, 0, Serialized)
{
Or (HCNT, 0x02, HCNT) // Send Kill
Or (HSTS, 0xff, HSTS) // Clean Status
}
// Check if last operation completed
// return Failure = 0, Success = 1
Method (CMPL, 0, Serialized)
{
Store (4000, Local0) // Timeout 200ms in 50us steps
While (Local0) {
If (And(HSTS, 0x02)) { // Completion Status?
Return (1) // Operation Completed
} Else {
Stall (50)
Decrement (Local0)
If (LEqual(Local0, 0)) {
KILL()
}
}
}
Return (0) // Failure
}
// Wait for SMBus to become ready
Method (SRDY, 0, Serialized)
{
Store (200, Local0) // Timeout 200ms
While (Local0) {
If (And(HSTS, 0x40)) { // IN_USE?
Sleep(1) // Wait 1ms
Decrement(Local0) // timeout--
If (LEqual(Local0, 0)) {
Return (1)
}
} Else {
Store (0, Local0) // We're ready
}
}
Store (4000, Local0) // Timeout 200ms (50us * 4000)
While (Local0) {
If (And (HSTS, 0x01)) { // Host Busy?
Stall(50) // Wait 50us
Decrement(Local0) // timeout--
If (LEqual(Local0, 0)) {
KILL()
}
} Else {
Return (0) // Success
}
}
Return (1) // Failure
}
// SMBus Send Byte
// Arg0: Address
// Arg1: Data
// Return: 1 = Success, 0=Failure
Method (SSXB, 2, Serialized)
{
// Is the SMBus Controller Ready?
If (SRDY()) {
Return (0)
}
// Send Byte
Store (0, I2CE) // SMBus Enable
Store (0xbf, HSTS)
Store (Arg0, TXSA) // Write Address
Store (Arg1, HCMD) // Write Data
Store (0x48, HCNT) // Start + Byte Data Protocol
If (CMPL()) {
Or (HSTS, 0xff, HSTS) // Clean up
Return (1) // Success
}
Return (0)
}
// SMBus Receive Byte
// Arg0: Address
// Return: 0xffff = Failure, Data (8bit) = Success
Method (SRXB, 2, Serialized)
{
// Is the SMBus Controller Ready?
If (SRDY()) {
Return (0xffff)
}
// Receive Byte
Store (0, I2CE) // SMBus Enable
Store (0xbf, HSTS)
Store (Or (Arg0, 1), TXSA) // Write Address
Store (0x44, HCNT) // Start
If (CMPL()) {
Or (HSTS, 0xff, HSTS) // Clean up
Return (DAT0) // Success
}
Return (0xffff)
}
// SMBus Write Byte
// Arg0: Address
// Arg1: Command
// Arg2: Data
// Return: 1 = Success, 0=Failure
Method (SWRB, 3, Serialized)
{
// Is the SMBus Controller Ready?
If (SRDY()) {
Return (0)
}
// Send Byte
Store (0, I2CE) // SMBus Enable
Store (0xbf, HSTS)
Store (Arg0, TXSA) // Write Address
Store (Arg1, HCMD) // Write Command
Store (Arg2, DAT0) // Write Data
Store (0x48, HCNT) // Start + Byte Protocol
If (CMPL()) {
Or (HSTS, 0xff, HSTS) // Clean up
Return (1) // Success
}
Return (0)
}
// SMBus Read Byte
// Arg0: Address
// Arg1: Command
// Return: 0xffff = Failure, Data (8bit) = Success
Method (SRDB, 2, Serialized)
{
// Is the SMBus Controller Ready?
If (SRDY()) {
Return (0xffff)
}
// Receive Byte
Store (0, I2CE) // SMBus Enable
Store (0xbf, HSTS)
Store (Or (Arg0, 1), TXSA) // Write Address
Store (Arg1, HCMD) // Command
Store (0x48, HCNT) // Start
If (CMPL()) {
Or (HSTS, 0xff, HSTS) // Clean up
Return (DAT0) // Success
}
Return (0xffff)
}
// Todo: Does anyone ever use these?
// Missing: Read / Write Word
// Missing: Read / Write Block
}

217
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* Intel i82801G USB support */
// USB Controller 0:1d.0
Device (USB1)
{
Name(_ADR, 0x001d0000)
OperationRegion(U01P, PCI_Config, 0, 256)
Field(U01P, DWordAcc, NoLock, Preserve)
{
Offset(0xc4),
U1WE, 2 // USB Wake Enable
}
Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
Method (_PSW, 1) // Power State Wake method
{
// USB Controller can wake OS from Sleep State
If (Arg0) {
Store (3, U1WE)
} Else {
Store (0, U1WE)
}
}
// Leave USB ports on for to allow Wake from USB
Method(_S3D,0) // Highest D State in S3 State
{
Return (2)
}
Method(_S4D,0) // Highest D State in S4 State
{
Return (2)
}
}
// USB Controller 0:1d.1
Device (USB2)
{
Name(_ADR, 0x001d0001)
OperationRegion(U02P, PCI_Config, 0, 256)
Field(U02P, DWordAcc, NoLock, Preserve)
{
Offset(0xc4),
U2WE, 2 // USB Wake Enable
}
Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
Method (_PSW, 1) // Power State Wake method
{
// USB Controller can wake OS from Sleep State
If (Arg0) {
Store (3, U2WE)
} Else {
Store (0, U2WE)
}
}
// Leave USB ports on for to allow Wake from USB
Method(_S3D,0) // Highest D State in S3 State
{
Return (2)
}
Method(_S4D,0) // Highest D State in S4 State
{
Return (2)
}
}
// USB Controller 0:1d.2
Device (USB3)
{
Name(_ADR, 0x001d0002)
OperationRegion(U03P, PCI_Config, 0, 256)
Field(U03P, DWordAcc, NoLock, Preserve)
{
Offset(0xc4),
U3WE, 2 // USB Wake Enable
}
Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
Method (_PSW, 1) // Power State Wake method
{
// USB Controller can wake OS from Sleep State
If (Arg0) {
Store (3, U3WE)
} Else {
Store (0, U3WE)
}
}
// Leave USB ports on for to allow Wake from USB
Method(_S3D,0) // Highest D State in S3 State
{
Return (2)
}
Method(_S4D,0) // Highest D State in S4 State
{
Return (2)
}
}
// USB Controller 0:1d.3
Device (USB4)
{
Name(_ADR, 0x001d0003)
OperationRegion(U04P, PCI_Config, 0, 256)
Field(U04P, DWordAcc, NoLock, Preserve)
{
Offset(0xc4),
U4WE, 2 // USB Wake Enable
}
Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
Method (_PSW, 1) // Power State Wake method
{
// USB Controller can wake OS from Sleep State
If (Arg0) {
Store (3, U4WE)
} Else {
Store (0, U4WE)
}
}
// Leave USB ports on for to allow Wake from USB
Method(_S3D,0) // Highest D State in S3 State
{
Return (2)
}
Method(_S4D,0) // Highest D State in S4 State
{
Return (2)
}
}
// EHCI Controller 0:1d.7
Device (EHC1)
{
Name(_ADR, 0x001d0007)
Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
// Leave USB ports on for to allow Wake from USB
Method(_S3D,0) // Highest D State in S3 State
{
Return (2)
}
Method(_S4D,0) // Highest D State in S4 State
{
Return (2)
}
Device (HUB7)
{
Name (_ADR, 0x00000000)
// How many are there?
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
Device (PRT2) { Name (_ADR, 2) } // USB Port 1
Device (PRT3) { Name (_ADR, 3) } // USB Port 2
Device (PRT4) { Name (_ADR, 4) } // USB Port 3
Device (PRT5) { Name (_ADR, 5) } // USB Port 4
Device (PRT6) { Name (_ADR, 6) } // USB Port 5
}
}