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soc/braswell: Add interface to program USB2_COMPBG register

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Add interface to program USB2_COMPBG register to set
HS_DISC_BG and HS_SQ reference voltage for each project.

TEST=Get build success and do EFT test

Original-Reviewed-on: https://chromium-review.googlesource.com/300846
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: shkim <sh_.kim@samsung.com>
Change-Id: If2201829e1a16b4f9916547f08c24e9291358325
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Signed-off-by: shkim <sh_.kim@samsung.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12739
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
shkim
2015-09-22 17:53:58 +09:00
committed by Martin Roth
parent e8cc52fab0
commit cc728f0284
5 changed files with 107 additions and 1 deletions
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20
src/soc/intel/braswell/chip.h
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@@ -38,6 +38,18 @@ enum lpe_clk_src {
LPE_CLK_SRC_PLL,
};
enum usb_comp_bg_value {
USB_COMP_BG_575_MV = 7,
USB_COMP_BG_650_MV = 6,
USB_COMP_BG_550_MV = 5,
USB_COMP_BG_537_MV = 4,
USB_COMP_BG_625_MV = 3,
USB_COMP_BG_700_MV = 2,
USB_COMP_BG_600_MV = 1,
USB_COMP_BG_675_MV = 0,
};
struct soc_intel_braswell_config {
uint8_t enable_xdp_tap;
uint8_t clkreq_enable;
@@ -61,6 +73,14 @@ struct soc_intel_braswell_config {
/* Allow PCIe devices to wake system from suspend. */
int pcie_wake_enable;
/* Program USB2_COMPBG register.
* [10:7] - select vref to AFE port
* x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV,
* x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV
*/
enum usb_comp_bg_value usb_comp_bg;
/*
* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
* These are configuration values that are passed to FSP during