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soc/intel/common: Move support to log XHCI wake events

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The policy to identify and log the XHCI wake events is similar between
skylake and apollolake. Hence move the similar parts to a common
location.

BUG=b:123429132
BRANCH=None
TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up
events due to USB are logged into the event logs.
6 | 2019-03-21 09:22:18 | S0ix Enter
7 | 2019-03-21 09:22:22 | S0ix Exit
8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9
9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13
10 | 2019-03-21 09:23:20 | ACPI Enter | S3
11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9
12 | 2019-03-21 09:23:30 | ACPI Wake | S3
13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13

Change-Id: Ia6643342e3292984e422ff3c3fcd4bc0d99f947e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian
2019-03-20 11:38:01 -06:00
committed by Patrick Georgi
parent e2ac5b7a36
commit cc7cdb19b1
6 changed files with 205 additions and 137 deletions
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1
src/soc/intel/skylake/Kconfig
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@@ -66,6 +66,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET