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soc/amd/picasso: Configure APOB NV only with ACPI resume

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The APOB NV region holds the save data for resuming.  Omit it if the
mainboard doesn't use HAVE_ACPI_RESUME.

The APOB information will also be board-specific so remove the
default values.

Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson
2019-12-12 12:38:45 -07:00
committed by Patrick Georgi
parent da6170a223
commit cca7486120
2 changed files with 2 additions and 6 deletions
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6
src/soc/amd/picasso/Kconfig
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@@ -297,21 +297,15 @@ config PSP_APOB_DESTINATION
config PSP_APOB_NV_ADDRESS config PSP_APOB_NV_ADDRESS
hex "Base address of APOB NV" hex "Base address of APOB NV"
default 0xffa68000
help help
Location in flash where the PSP can find the S3 restore information. Location in flash where the PSP can find the S3 restore information.
Place this on a boundary that the flash device can erase. Place this on a boundary that the flash device can erase.
TODO: The above default value is arbitrary, but eventually coreboot's
MRC cache base address should be used.
config PSP_APOB_NV_SIZE config PSP_APOB_NV_SIZE
hex "Size of APOB NV to be reserved" hex "Size of APOB NV to be reserved"
default 0x10000
help help
Size of the S3 restore information. Make this a multiple of the Size of the S3 restore information. Make this a multiple of the
size the flash device can erase. size the flash device can erase.
TODO: The above default value is arbitrary, but eventually coreboot's
MRC cache size should be used.
config USE_PSPSCUREOS config USE_PSPSCUREOS
bool "Include PSP SecureOS blobs in PSP build" bool "Include PSP SecureOS blobs in PSP build"

2
src/soc/amd/picasso/Makefile.inc
View File

@@ -207,8 +207,10 @@ PSP_BIOSBIN_DEST=$(CONFIG_ROMSTAGE_ADDR)
PSP_BIOSBIN_SIZE=$(CONFIG_RAM_RESET_VECTOR_STAGE_SIZE) PSP_BIOSBIN_SIZE=$(CONFIG_RAM_RESET_VECTOR_STAGE_SIZE)
# type = 0x63 # type = 0x63
ifeq ($(CONFIG_HAVE_ACPI_RESUME),y)
PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS) PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS)
PSP_APOBNV_SIZE=$(CONFIG_PSP_APOB_NV_SIZE) PSP_APOBNV_SIZE=$(CONFIG_PSP_APOB_NV_SIZE)
endif
# type2 = 0x64, 0x65 # type2 = 0x64, 0x65
PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin