soc/intel/tigerlake: Add PCH-H root ports
Change-Id: I89e300adce2edeb9d9c2bba1782c212ee656a532
This commit is contained in:
committed by
Tim Crawford
parent
14d84624eb
commit
cca90d8090
@@ -18,6 +18,13 @@ Name (PICP, Package () {
|
||||
Package(){0x001CFFFF, 1, 0, 17 },
|
||||
Package(){0x001CFFFF, 2, 0, 18 },
|
||||
Package(){0x001CFFFF, 3, 0, 19 },
|
||||
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
|
||||
/* D27 */
|
||||
Package(){0x001BFFFF, 0, 0, 16 },
|
||||
Package(){0x001BFFFF, 1, 0, 17 },
|
||||
Package(){0x001BFFFF, 2, 0, 18 },
|
||||
Package(){0x001BFFFF, 3, 0, 19 },
|
||||
#endif
|
||||
/* D25 */
|
||||
Package(){0x0019FFFF, 0, 0, 31 },
|
||||
Package(){0x0019FFFF, 1, 0, 32 },
|
||||
@@ -73,6 +80,10 @@ Name (PICP, Package () {
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* D2 */
|
||||
Package(){0x0002FFFF, 0, 0, 16 },
|
||||
/* D1 */
|
||||
Package(){0x0001FFFF, 0, 0, 16 },
|
||||
Package(){0x0001FFFF, 1, 0, 17 },
|
||||
Package(){0x0001FFFF, 2, 0, 18 },
|
||||
})
|
||||
|
||||
Name (PICN, Package () {
|
||||
@@ -93,6 +104,13 @@ Name (PICN, Package () {
|
||||
Package(){0x001CFFFF, 1, 0, 10 },
|
||||
Package(){0x001CFFFF, 2, 0, 11 },
|
||||
Package(){0x001CFFFF, 3, 0, 11 },
|
||||
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
|
||||
/* D27 */
|
||||
Package () { 0x001BFFFF, 0, 0, 11 },
|
||||
Package () { 0x001BFFFF, 1, 0, 10 },
|
||||
Package () { 0x001BFFFF, 2, 0, 11 },
|
||||
Package () { 0x001BFFFF, 3, 0, 11 },
|
||||
#endif
|
||||
/* D25 */
|
||||
Package(){0x0019FFFF, 0, 0, 11 },
|
||||
Package(){0x0019FFFF, 1, 0, 10 },
|
||||
@@ -148,6 +166,10 @@ Name (PICN, Package () {
|
||||
Package(){0x0004FFFF, 0, 0, 11 },
|
||||
/* D2 */
|
||||
Package(){0x0002FFFF, 0, 0, 11 },
|
||||
/* D1 */
|
||||
Package(){0x0001FFFF, 0, 0, 11 },
|
||||
Package(){0x0001FFFF, 1, 0, 10 },
|
||||
Package(){0x0001FFFF, 2, 0, 11 },
|
||||
})
|
||||
|
||||
Method (_PRT)
|
||||
|
@@ -54,7 +54,11 @@ Method (IRQM, 1, Serialized) {
|
||||
|
||||
Switch (ToInteger (Arg0))
|
||||
{
|
||||
Case (Package () { 1, 5, 9, 13 }) {
|
||||
Case (Package () { 1, 5, 9, 13
|
||||
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
|
||||
, 17, 21
|
||||
#endif
|
||||
}) {
|
||||
If (PICM) {
|
||||
Return (IQAA)
|
||||
} Else {
|
||||
@@ -62,7 +66,11 @@ Method (IRQM, 1, Serialized) {
|
||||
}
|
||||
}
|
||||
|
||||
Case (Package () { 2, 6, 10, 14 }) {
|
||||
Case (Package () { 2, 6, 10, 14
|
||||
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
|
||||
, 18, 22
|
||||
#endif
|
||||
}) {
|
||||
If (PICM) {
|
||||
Return (IQBA)
|
||||
} Else {
|
||||
@@ -70,7 +78,11 @@ Method (IRQM, 1, Serialized) {
|
||||
}
|
||||
}
|
||||
|
||||
Case (Package () { 3, 7, 11, 15 }) {
|
||||
Case (Package () { 3, 7, 11, 15
|
||||
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
|
||||
, 19, 23
|
||||
#endif
|
||||
}) {
|
||||
If (PICM) {
|
||||
Return (IQCA)
|
||||
} Else {
|
||||
@@ -78,7 +90,11 @@ Method (IRQM, 1, Serialized) {
|
||||
}
|
||||
}
|
||||
|
||||
Case (Package () { 4, 8, 12, 16 }) {
|
||||
Case (Package () { 4, 8, 12, 16
|
||||
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
|
||||
, 20, 24
|
||||
#endif
|
||||
}) {
|
||||
If (PICM) {
|
||||
Return (IQDA)
|
||||
} Else {
|
||||
@@ -304,3 +320,141 @@ Device (RP12)
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
|
||||
Device (RP17)
|
||||
{
|
||||
Name (_ADR, 0x001B0000)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP18)
|
||||
{
|
||||
Name (_ADR, 0x001B0001)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP19)
|
||||
{
|
||||
Name (_ADR, 0x001B0002)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP20)
|
||||
{
|
||||
Name (_ADR, 0x001B0003)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP21)
|
||||
{
|
||||
Name (_ADR, 0x001B0004)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP22)
|
||||
{
|
||||
Name (_ADR, 0x001B0005)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP23)
|
||||
{
|
||||
Name (_ADR, 0x001B0006)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP24)
|
||||
{
|
||||
Name (_ADR, 0x001B0007)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
@@ -24,6 +24,13 @@ static const struct pcie_rp_group pch_lp_rp_groups[] = {
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
static const struct pcie_rp_group pch_h_rp_groups[] = {
|
||||
{ .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
|
||||
{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
|
||||
{ .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
#if CONFIG(HAVE_ACPI_TABLES)
|
||||
const char *soc_acpi_name(const struct device *dev)
|
||||
{
|
||||
@@ -95,6 +102,18 @@ const char *soc_acpi_name(const struct device *dev)
|
||||
case PCH_DEVFN_PCIE10: return "RP10";
|
||||
case PCH_DEVFN_PCIE11: return "RP11";
|
||||
case PCH_DEVFN_PCIE12: return "RP12";
|
||||
case PCH_DEVFN_PCIE13: return "RP13";
|
||||
case PCH_DEVFN_PCIE14: return "RP14";
|
||||
case PCH_DEVFN_PCIE15: return "RP15";
|
||||
case PCH_DEVFN_PCIE16: return "RP16";
|
||||
case PCH_DEVFN_PCIE17: return "RP17";
|
||||
case PCH_DEVFN_PCIE18: return "RP18";
|
||||
case PCH_DEVFN_PCIE19: return "RP19";
|
||||
case PCH_DEVFN_PCIE20: return "RP20";
|
||||
case PCH_DEVFN_PCIE21: return "RP21";
|
||||
case PCH_DEVFN_PCIE22: return "RP22";
|
||||
case PCH_DEVFN_PCIE23: return "RP23";
|
||||
case PCH_DEVFN_PCIE24: return "RP24";
|
||||
case PCH_DEVFN_PMC: return "PMC";
|
||||
case PCH_DEVFN_UART0: return "UAR0";
|
||||
case PCH_DEVFN_UART1: return "UAR1";
|
||||
@@ -146,7 +165,10 @@ void soc_init_pre_device(void *chip_info)
|
||||
soc_fill_gpio_pm_configuration();
|
||||
|
||||
/* Swap enabled PCI ports in device tree if needed. */
|
||||
pcie_rp_update_devicetree(pch_lp_rp_groups);
|
||||
if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H))
|
||||
pcie_rp_update_devicetree(pch_h_rp_groups);
|
||||
else
|
||||
pcie_rp_update_devicetree(pch_lp_rp_groups);
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
|
@@ -157,10 +157,36 @@
|
||||
#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
|
||||
#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
|
||||
#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
|
||||
#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4)
|
||||
#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5)
|
||||
#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6)
|
||||
#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7)
|
||||
#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)
|
||||
#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)
|
||||
#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)
|
||||
#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)
|
||||
#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4)
|
||||
#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5)
|
||||
#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6)
|
||||
#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7)
|
||||
|
||||
#define PCH_DEV_SLOT_PCIE_2 0x1b
|
||||
#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0)
|
||||
#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1)
|
||||
#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2)
|
||||
#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3)
|
||||
#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4)
|
||||
#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5)
|
||||
#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6)
|
||||
#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7)
|
||||
#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0)
|
||||
#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1)
|
||||
#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2)
|
||||
#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3)
|
||||
#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4)
|
||||
#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5)
|
||||
#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6)
|
||||
#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7)
|
||||
|
||||
#define PCH_DEV_SLOT_SIO5 0x1e
|
||||
#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0)
|
||||
|
Reference in New Issue
Block a user