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soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFN

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Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.

BRANCH=None
BUG=None
TEST=Built and tested on dedede board

Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet R Pawnikar
2020-09-11 18:51:36 +05:30
committed by Patrick Georgi
parent e5655a11d2
commit ccbe5307d8
4 changed files with 3 additions and 8 deletions
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4
src/soc/intel/jasperlake/fsp_params.c
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@@ -183,7 +183,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
if (params->ScsSdCardEnabled)
params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
params->Device4Enable = config->Device4Enable;
/* Enable Processor Thermal Control */
dev = pcidev_path_on_root(SA_DEVFN_DPTF);
params->Device4Enable = is_dev_enabled(dev);
/* Set TccActivationOffset */
params->TccActivationOffset = config->tcc_offset;