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soc/intel/apollolake: Use common PCR module

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This patch use common PCR library to perform CRRd and CRWr operation
using Port Ids, define inside soc/pcr_ids.h

Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18673
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik
2017-03-08 17:55:26 +05:30
committed by Martin Roth
parent e7ceae7950
commit ccd8700cac
11 changed files with 106 additions and 135 deletions
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8
src/soc/intel/apollolake/Kconfig
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@@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
# CPU specific options
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select IOAPIC
select PCR_COMMON_IOSF_1_0
select SMP
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
@@ -52,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_SMI
@@ -91,9 +93,11 @@ config SOC_INTEL_COMMON_RESET
bool
default y
config IOSF_BASE_ADDRESS
hex "MMIO Base Address of sideband bus"
config PCR_BASE_ADDRESS
hex
default 0xd0000000
help
This option allows you to select MMIO Base Address of sideband bus.
config DCACHE_RAM_BASE
hex "Base address of cache-as-RAM"