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cpu/amd/geode_lx: Reduce fancy ASCII art with embedded comments

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Lets try not to play games with the Lexer with fancy ASCII art. Doxygen
has a more well defined and useful syntax for annotations.

Change-Id: I6f6c58971f509064ae1e28a1740e50e2ae721513
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6550
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Edward O'Callaghan
2014-08-09 15:51:19 +10:00
parent 728ff392e7
commit cd2c1245f0
4 changed files with 27 additions and 42 deletions
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11
src/cpu/amd/geode_lx/cache_as_ram.inc
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@ -25,15 +25,14 @@
#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) #define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
/***************************************************************************
/** /**
/** DCacheSetup * DCacheSetup
/** * Setup data cache for use as RAM for a stack.
/** Setup data cache for use as RAM for a stack. */
/**
/***************************************************************************/
DCacheSetup: DCacheSetup:
/* Save the BIST result */ /* Save the BIST result */
movl %eax, %ebx movl %eax, %ebx

28
src/cpu/amd/geode_lx/cpubug.c
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@ -29,15 +29,15 @@
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
/************************************************************************** /**
* *
* pcideadlock * pcideadlock
* *
* Bugtool #465 and #609 * Bugtool #465 and #609
* PCI cache deadlock * PCI cache deadlock
* There is also fix code in cache and PCI functions. This bug is very is pervasive. * There is also fix code in cache and PCI functions.
* * This bug is very is pervasive.
**************************************************************************/ */
static void pcideadlock(void) static void pcideadlock(void)
{ {
msr_t msr; msr_t msr;
@ -61,17 +61,15 @@ static void pcideadlock(void)
wrmsr(CPU_RCONF_E0_FF, msr); wrmsr(CPU_RCONF_E0_FF, msr);
} }
/****************************************************************************/ /**
/***/ * DisableMemoryReorder
/** DisableMemoryReorder*/ *
/***/ * PBZ 3659:
/** PBZ 3659:*/ * The MC reordered transactions incorrectly and breaks coherency.
/** The MC reordered transactions incorrectly and breaks coherency.*/ * Disable reordering and take a potential performance hit.
/** Disable reordering and take a potential performance hit.*/ * This is safe to do here and not in MC init since there is nothing
/** This is safe to do here and not in MC init since there is nothing*/ * to maintain coherency with and the cache is not enabled yet.
/** to maintain coherency with and the cache is not enabled yet.*/ */
/***/
/****************************************************************************/
static void disablememoryreadorder(void) static void disablememoryreadorder(void)
{ {
msr_t msr; msr_t msr;

14
src/cpu/amd/geode_lx/cpureginit.c
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@ -20,16 +20,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/************************************************************************** /* SetDelayControl */
;*
;* SetDelayControl
;*
;*************************************************************************/
#include "cpu/x86/msr.h" #include "cpu/x86/msr.h"
/** /**
* Delay Control Settings table from AMD (MCP 0x4C00000F). * Delay Control Settings table from AMD (MCP 0x4C00000F).
*/ */
@ -39,8 +33,6 @@ static const msrinit_t delay_msr_table[] = {
{CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}}, {CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}},
}; };
static const struct delay_controls { static const struct delay_controls {
u8 dimms; u8 dimms;
u8 devices; u8 devices;
@ -171,9 +163,7 @@ static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated)
wrmsr(GLCP_DELAY_CONTROLS, msr); wrmsr(GLCP_DELAY_CONTROLS, msr);
} }
/* ***************************************************************************/ /* cpuRegInit */
/* * cpuRegInit*/
/* ***************************************************************************/
void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
{ {
int msrnum; int msrnum;

16
src/cpu/amd/geode_lx/syspreinit.c
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@ -20,15 +20,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/* ***************************************************************************/ /**
/* **/ * StartTimer1
/* * StartTimer1*/ *
/* **/ * Entry: none
/* * Entry: none*/ * Exit: Starts Timer 1 for port 61 use
/* * Exit: Starts Timer 1 for port 61 use*/ * Destroys: Al,
/* * Destroys: Al,*/ */
/* **/
/* ***************************************************************************/
static void StartTimer1(void) static void StartTimer1(void)
{ {
outb(0x56, 0x43); outb(0x56, 0x43);