cpu/amd/geode_lx: Reduce fancy ASCII art with embedded comments
Lets try not to play games with the Lexer with fancy ASCII art. Doxygen has a more well defined and useful syntax for annotations. Change-Id: I6f6c58971f509064ae1e28a1740e50e2ae721513 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6550 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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@ -25,15 +25,14 @@
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#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
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#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
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#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
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#include <cpu/amd/lxdef.h>
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#include <cpu/x86/post_code.h>
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/***************************************************************************
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/**
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/** DCacheSetup
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/**
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/** Setup data cache for use as RAM for a stack.
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/**
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/***************************************************************************/
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* DCacheSetup
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* Setup data cache for use as RAM for a stack.
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*/
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DCacheSetup:
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/* Save the BIST result */
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movl %eax, %ebx
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@ -29,15 +29,15 @@
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#include <cpu/x86/msr.h>
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#include <cpu/amd/lxdef.h>
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/**************************************************************************
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/**
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*
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* pcideadlock
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*
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* Bugtool #465 and #609
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* PCI cache deadlock
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* There is also fix code in cache and PCI functions. This bug is very is pervasive.
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*
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**************************************************************************/
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* There is also fix code in cache and PCI functions.
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* This bug is very is pervasive.
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*/
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static void pcideadlock(void)
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{
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msr_t msr;
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@ -61,17 +61,15 @@ static void pcideadlock(void)
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wrmsr(CPU_RCONF_E0_FF, msr);
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}
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/****************************************************************************/
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/***/
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/** DisableMemoryReorder*/
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/***/
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/** PBZ 3659:*/
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/** The MC reordered transactions incorrectly and breaks coherency.*/
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/** Disable reordering and take a potential performance hit.*/
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/** This is safe to do here and not in MC init since there is nothing*/
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/** to maintain coherency with and the cache is not enabled yet.*/
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/***/
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/****************************************************************************/
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/**
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* DisableMemoryReorder
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*
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* PBZ 3659:
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* The MC reordered transactions incorrectly and breaks coherency.
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* Disable reordering and take a potential performance hit.
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* This is safe to do here and not in MC init since there is nothing
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* to maintain coherency with and the cache is not enabled yet.
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*/
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static void disablememoryreadorder(void)
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{
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msr_t msr;
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@ -20,16 +20,10 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**************************************************************************
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;*
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;* SetDelayControl
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;*
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;*************************************************************************/
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/* SetDelayControl */
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#include "cpu/x86/msr.h"
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/**
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* Delay Control Settings table from AMD (MCP 0x4C00000F).
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*/
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@ -39,8 +33,6 @@ static const msrinit_t delay_msr_table[] = {
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{CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}},
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};
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static const struct delay_controls {
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u8 dimms;
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u8 devices;
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@ -171,9 +163,7 @@ static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated)
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wrmsr(GLCP_DELAY_CONTROLS, msr);
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}
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/* ***************************************************************************/
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/* * cpuRegInit*/
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/* ***************************************************************************/
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/* cpuRegInit */
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void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
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{
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int msrnum;
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@ -20,15 +20,13 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* ***************************************************************************/
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/* **/
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/* * StartTimer1*/
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/* **/
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/* * Entry: none*/
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/* * Exit: Starts Timer 1 for port 61 use*/
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/* * Destroys: Al,*/
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/* **/
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/* ***************************************************************************/
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/**
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* StartTimer1
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*
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* Entry: none
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* Exit: Starts Timer 1 for port 61 use
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* Destroys: Al,
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*/
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static void StartTimer1(void)
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{
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outb(0x56, 0x43);
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