coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Patrick Georgi
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cd49cce7b7
@@ -103,7 +103,7 @@ static void load_vectors(void *ioapic_base)
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ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
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if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_FSB)) {
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if (CONFIG(IOAPIC_INTERRUPTS_ON_FSB)) {
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/*
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* For the Pentium 4 and above APICs deliver their interrupts
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* on the front side bus, enable that.
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@@ -111,7 +111,7 @@ static void load_vectors(void *ioapic_base)
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printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
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io_apic_write(ioapic_base, 0x03,
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io_apic_read(ioapic_base, 0x03) | (1 << 0));
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} else if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) {
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} else if (CONFIG(IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) {
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printk(BIOS_DEBUG,
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"IOAPIC: Enabling interrupts on APIC serial bus\n");
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io_apic_write(ioapic_base, 0x03, 0);
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