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coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

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This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julius Werner
2019-03-05 16:53:33 -08:00
committed by Patrick Georgi
parent b3a8cc54db
commit cd49cce7b7
920 changed files with 2285 additions and 2285 deletions
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24
src/console/post.c
View File

@ -20,7 +20,7 @@
#include <device/device.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#if IS_ENABLED(CONFIG_POST_IO)
#if CONFIG(POST_IO)
#include <arch/io.h>
#endif
@ -40,7 +40,7 @@ void __weak mainboard_post(uint8_t value)
#define mainboard_post(x)
#endif
#if IS_ENABLED(CONFIG_CMOS_POST)
#if CONFIG(CMOS_POST)
DECLARE_SPIN_LOCK(cmos_post_lock)
@ -48,7 +48,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock)
void cmos_post_log(void)
{
u8 code = 0;
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
u32 extra = 0;
#endif
@ -58,13 +58,13 @@ void cmos_post_log(void)
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
case CMOS_POST_BANK_0_MAGIC:
code = cmos_read(CMOS_POST_BANK_1_OFFSET);
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
extra = cmos_read32(CMOS_POST_BANK_1_EXTRA);
#endif
break;
case CMOS_POST_BANK_1_MAGIC:
code = cmos_read(CMOS_POST_BANK_0_OFFSET);
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
extra = cmos_read32(CMOS_POST_BANK_0_EXTRA);
#endif
break;
@ -82,9 +82,9 @@ void cmos_post_log(void)
default:
printk(BIOS_WARNING, "POST: Unexpected post code "
"in previous boot: 0x%02x\n", code);
#if IS_ENABLED(CONFIG_ELOG)
#if CONFIG(ELOG)
elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code);
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
if (extra)
elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra);
#endif
@ -92,7 +92,7 @@ void cmos_post_log(void)
}
}
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
void post_log_extra(u32 value)
{
spin_lock(&cmos_post_lock);
@ -146,14 +146,14 @@ static void cmos_post_code(u8 value)
void post_code(uint8_t value)
{
#if !IS_ENABLED(CONFIG_NO_POST)
#if IS_ENABLED(CONFIG_CONSOLE_POST)
#if !CONFIG(NO_POST)
#if CONFIG(CONSOLE_POST)
printk(BIOS_EMERG, "POST: 0x%02x\n", value);
#endif
#if IS_ENABLED(CONFIG_CMOS_POST)
#if CONFIG(CMOS_POST)
cmos_post_code(value);
#endif
#if IS_ENABLED(CONFIG_POST_IO)
#if CONFIG(POST_IO)
outb(value, CONFIG_POST_IO_PORT);
#endif
#endif