coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julius Werner
2019-03-05 16:53:33 -08:00
committed by Patrick Georgi
parent b3a8cc54db
commit cd49cce7b7
920 changed files with 2285 additions and 2285 deletions

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@@ -26,7 +26,7 @@
* lizations automatically. When not, we have to call it explicitly.
*/
#if IS_ENABLED(CONFIG_RAMSTAGE_ADA)
#if CONFIG(RAMSTAGE_ADA)
void ramstage_adainit(void);
#else
static inline void ramstage_adainit(void) {}

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@@ -24,14 +24,14 @@
if (!(x)) { \
printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \
", line %d\n", __FILE__, __LINE__); \
if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) \
if (CONFIG(FATAL_ASSERTS)) \
hlt(); \
} \
}
#define BUG() { \
printk(BIOS_EMERG, "ERROR: BUG ENCOUNTERED at file '%s'"\
", line %d\n", __FILE__, __LINE__); \
if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) \
if (CONFIG(FATAL_ASSERTS)) \
hlt(); \
}

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@@ -115,12 +115,12 @@ struct boot_state_callback {
void (*callback)(void *arg);
/* For use internal to the boot state machine. */
struct boot_state_callback *next;
#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)
#if CONFIG(DEBUG_BOOT_STATE)
const char *location;
#endif
};
#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)
#if CONFIG(DEBUG_BOOT_STATE)
#define BOOT_STATE_CALLBACK_LOC __FILE__ ":" STRINGIFY(__LINE__)
#define BOOT_STATE_CALLBACK_INIT_DEBUG .location = BOOT_STATE_CALLBACK_LOC,
#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \

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@@ -155,7 +155,7 @@ void cbmem_add_records_to_cbtable(struct lb_header *header);
* and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top()
* value stored in nvram to enable early recovery on S3 path.
*/
#if IS_ENABLED(CONFIG_ARCH_X86)
#if CONFIG(ARCH_X86)
void backup_top_of_low_cacheable(uintptr_t ramtop);
uintptr_t restore_top_of_low_cacheable(void);
#endif
@@ -170,7 +170,7 @@ static inline int cbmem_possibly_online(void)
if (ENV_BOOTBLOCK)
return 0;
if (ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
if (ENV_VERSTAGE && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))
return 0;
return 1;

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@@ -20,9 +20,9 @@
void cbmemc_init(void);
void cbmemc_tx_byte(unsigned char data);
#define __CBMEM_CONSOLE_ENABLE__ (IS_ENABLED(CONFIG_CONSOLE_CBMEM) && \
#define __CBMEM_CONSOLE_ENABLE__ (CONFIG(CONSOLE_CBMEM) && \
(ENV_RAMSTAGE || ENV_VERSTAGE || ENV_POSTCAR || ENV_ROMSTAGE || \
(ENV_BOOTBLOCK && IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE))))
(ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE))))
#if __CBMEM_CONSOLE_ENABLE__
static inline void __cbmemc_init(void) { cbmemc_init(); }

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@@ -22,13 +22,13 @@
#include <console/vtxprintf.h>
#include <commonlib/loglevel.h>
#define RAM_DEBUG (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER)
#define RAM_SPEW (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER)
#define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER)
#define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER)
#ifndef __ROMCC__
void post_code(u8 value);
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
void post_log_extra(u32 value);
struct device;
void post_log_path(const struct device *dev);
@@ -49,10 +49,10 @@ void __noreturn die(const char *msg);
void die_notify(void);
#define __CONSOLE_ENABLE__ \
((ENV_BOOTBLOCK && IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) || \
(ENV_POSTCAR && IS_ENABLED(CONFIG_POSTCAR_CONSOLE)) || \
((ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE)) || \
(ENV_POSTCAR && CONFIG(POSTCAR_CONSOLE)) || \
ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_LIBAGESA || \
(ENV_SMM && IS_ENABLED(CONFIG_DEBUG_SMI)))
(ENV_SMM && CONFIG(DEBUG_SMI)))
#if __CONSOLE_ENABLE__
asmlinkage void console_init(void);
@@ -64,7 +64,7 @@ void do_putchar(unsigned char byte);
enum { CONSOLE_LOG_NONE = 0, CONSOLE_LOG_FAST, CONSOLE_LOG_ALL };
#if IS_ENABLED(CONFIG_CONSOLE_OVERRIDE_LOGLEVEL)
#if CONFIG(CONSOLE_OVERRIDE_LOGLEVEL)
/*
* This function should be implemented at mainboard level.
* The returned value will _replace_ the loglevel value;

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@@ -22,7 +22,7 @@ void flashconsole_init(void);
void flashconsole_tx_byte(unsigned char c);
void flashconsole_tx_flush(void);
#define __CONSOLE_FLASH_ENABLE__ IS_ENABLED(CONFIG_CONSOLE_SPI_FLASH)
#define __CONSOLE_FLASH_ENABLE__ CONFIG(CONSOLE_SPI_FLASH)
#if __CONSOLE_FLASH_ENABLE__
static inline void __flashconsole_init(void) { flashconsole_init(); }

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@@ -22,7 +22,7 @@ void ne2k_append_data(unsigned char *d, int len, unsigned int base);
int ne2k_init(unsigned int eth_nic_base);
void ne2k_transmit(unsigned int eth_nic_base);
#if IS_ENABLED(CONFIG_CONSOLE_NE2K) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
#if CONFIG(CONSOLE_NE2K) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
static inline void __ne2k_init(void)
{
ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);

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@@ -6,7 +6,7 @@
void qemu_debugcon_init(void);
void qemu_debugcon_tx_byte(unsigned char data);
#if IS_ENABLED(CONFIG_CONSOLE_QEMU_DEBUGCON) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
#if CONFIG(CONSOLE_QEMU_DEBUGCON) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
static inline void __qemu_debugcon_init(void) { qemu_debugcon_init(); }
static inline void __qemu_debugcon_tx_byte(u8 data)
{

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@@ -21,8 +21,8 @@
void spiconsole_init(void);
void spiconsole_tx_byte(unsigned char c);
#define __CONSOLE_SPI_ENABLE__ (IS_ENABLED(CONFIG_SPI_CONSOLE) && \
(ENV_RAMSTAGE || (ENV_SMM && IS_ENABLED(CONFIG_DEBUG_SMI))))
#define __CONSOLE_SPI_ENABLE__ (CONFIG(SPI_CONSOLE) && \
(ENV_RAMSTAGE || (ENV_SMM && CONFIG(DEBUG_SMI))))
#if __CONSOLE_SPI_ENABLE__
static inline void __spiconsole_init(void) { spiconsole_init(); }

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@@ -6,7 +6,7 @@
void spkmodem_init(void);
void spkmodem_tx_byte(unsigned char c);
#if IS_ENABLED(CONFIG_SPKMODEM) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
#if CONFIG(SPKMODEM) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
static inline void __spkmodem_init(void) { spkmodem_init(); }
static inline void __spkmodem_tx_byte(u8 data) { spkmodem_tx_byte(data); }
#else

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@@ -22,7 +22,7 @@
* baudrate generator. */
unsigned int uart_platform_refclk(void);
#if IS_ENABLED(CONFIG_UART_OVERRIDE_BAUDRATE)
#if CONFIG(UART_OVERRIDE_BAUDRATE)
/* Return the baudrate, define this in your platform when using the above
configuration. */
unsigned int get_uart_baudrate(void);
@@ -63,9 +63,9 @@ static inline void *uart_platform_baseptr(int idx)
void oxford_remap(unsigned int new_base);
#define __CONSOLE_SERIAL_ENABLE__ (IS_ENABLED(CONFIG_CONSOLE_SERIAL) && \
#define __CONSOLE_SERIAL_ENABLE__ (CONFIG(CONSOLE_SERIAL) && \
(ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \
ENV_POSTCAR || (ENV_SMM && IS_ENABLED(CONFIG_DEBUG_SMI))))
ENV_POSTCAR || (ENV_SMM && CONFIG(DEBUG_SMI))))
#if __CONSOLE_SERIAL_ENABLE__
static inline void __uart_init(void)
@@ -86,7 +86,7 @@ static inline void __uart_tx_byte(u8 data) {}
static inline void __uart_tx_flush(void) {}
#endif
#if IS_ENABLED(CONFIG_GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
#if CONFIG(GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
#define CONF_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE
static inline void __gdb_hw_init(void) { uart_init(CONF_UART_FOR_GDB); }
static inline void __gdb_tx_byte(u8 data)

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@@ -27,10 +27,10 @@ void usb_tx_flush(int idx);
unsigned char usb_rx_byte(int idx);
int usb_can_rx_byte(int idx);
#define __CONSOLE_USB_ENABLE__ (IS_ENABLED(CONFIG_CONSOLE_USB) && \
((ENV_BOOTBLOCK && IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) || \
(ENV_ROMSTAGE && IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) || \
(ENV_POSTCAR && IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) || \
#define __CONSOLE_USB_ENABLE__ (CONFIG(CONSOLE_USB) && \
((ENV_BOOTBLOCK && CONFIG(USBDEBUG_IN_PRE_RAM)) || \
(ENV_ROMSTAGE && CONFIG(USBDEBUG_IN_PRE_RAM)) || \
(ENV_POSTCAR && CONFIG(USBDEBUG_IN_PRE_RAM)) || \
ENV_RAMSTAGE))
#define USB_PIPE_FOR_CONSOLE 0
@@ -50,8 +50,8 @@ static inline void __usb_tx_flush(void) {}
#endif
/* */
#if 0 && IS_ENABLED(CONFIG_GDB_STUB) && \
((ENV_ROMSTAGE && IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) \
#if 0 && CONFIG(GDB_STUB) && \
((ENV_ROMSTAGE && CONFIG(USBDEBUG_IN_PRE_RAM)) \
|| ENV_RAMSTAGE)
static inline void __gdb_hw_init(void) { usbdebug_init(); }
static inline void __gdb_tx_byte(u8 data)

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@@ -386,7 +386,7 @@ typedef struct cper_ia32x64_ctx_x64state {
static inline cper_timestamp_t cper_timestamp(int precise)
{
cper_timestamp_t ts;
#if IS_ENABLED(CONFIG_RTC)
#if CONFIG(RTC)
struct rtc_time time;
rtc_get(&time);

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@@ -45,7 +45,7 @@ static __always_inline unsigned long lapicid(void)
return lapic_read(LAPIC_ID) >> 24;
}
#if !IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT)
#if !CONFIG(AP_IN_SIPI_WAIT)
/* If we need to go back to sipi wait, we use the long non-inlined version of
* this function in lapic_cpu_init.c
*/
@@ -142,7 +142,7 @@ void do_lapic_init(void);
/* See if I need to initialize the local APIC */
static inline int need_lapic_init(void)
{
return IS_ENABLED(CONFIG_SMP) || IS_ENABLED(CONFIG_IOAPIC);
return CONFIG(SMP) || CONFIG(IOAPIC);
}
static inline void setup_lapic(void)

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@@ -105,7 +105,7 @@ typedef struct msrinit_struct {
msr_t msr;
} msrinit_t;
#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
#if CONFIG(SOC_SETS_MSRS)
msr_t soc_msr_read(unsigned int index);
void soc_msr_write(unsigned int index, msr_t msr);

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@@ -4,7 +4,7 @@
#include <console/post_codes.h>
#if IS_ENABLED(CONFIG_POST_IO)
#if CONFIG(POST_IO)
#define post_code(value) \
movb $value, %al; \
outb %al, $CONFIG_POST_IO_PORT

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@@ -486,7 +486,7 @@ int mainboard_io_trap_handler(int smif);
void southbridge_smi_set_eos(void);
#if IS_ENABLED(CONFIG_SMM_TSEG)
#if CONFIG(SMM_TSEG)
void cpu_smi_handler(void);
void northbridge_smi_handler(void);
void southbridge_smi_handler(void);
@@ -501,7 +501,7 @@ void mainboard_smi_gpi(u32 gpi_sts);
int mainboard_smi_apmc(u8 data);
void mainboard_smi_sleep(u8 slp_typ);
#if !IS_ENABLED(CONFIG_SMM_TSEG)
#if !CONFIG(SMM_TSEG)
void smi_release_lock(void);
#endif

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@@ -3,9 +3,9 @@
#include <stdint.h>
#if IS_ENABLED(CONFIG_TSC_SYNC_MFENCE)
#if CONFIG(TSC_SYNC_MFENCE)
#define TSC_SYNC "mfence\n"
#elif IS_ENABLED(CONFIG_TSC_SYNC_LFENCE)
#elif CONFIG(TSC_SYNC_LFENCE)
#define TSC_SYNC "lfence\n"
#else
#define TSC_SYNC

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@@ -52,12 +52,12 @@ struct device_operations {
void (*disable)(struct device *dev);
void (*set_link)(struct device *dev, unsigned int link);
void (*reset_bus)(struct bus *bus);
#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
#if CONFIG(GENERATE_SMBIOS_TABLES)
int (*get_smbios_data)(struct device *dev, int *handle,
unsigned long *current);
void (*get_smbios_strings)(struct device *dev, struct smbios_type11 *t);
#endif
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
unsigned long (*write_acpi_tables)(struct device *dev,
unsigned long start, struct acpi_rsdp *rsdp);
void (*acpi_fill_ssdt_generator)(struct device *dev);
@@ -158,7 +158,7 @@ extern struct bus *free_links;
extern const char mainboard_name[];
#if IS_ENABLED(CONFIG_GFXUMA)
#if CONFIG(GFXUMA)
/* IGD UMA memory */
extern uint64_t uma_memory_base;
extern uint64_t uma_memory_size;

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@@ -52,7 +52,7 @@
* disabled.
* @{
*/
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#if CONFIG(DEBUG_RAM_SETUP)
#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
#else
#define printram(x, ...)

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@@ -56,7 +56,7 @@
* disabled.
* @{
*/
#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#if CONFIG(DEBUG_RAM_SETUP)
#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
#else
#define printram(x, ...)

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@@ -52,7 +52,7 @@
/**
* \brief printk macro for SMBus debugging
*/
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
#if CONFIG(DEBUG_SMBUS)
#define printsmbus(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
#else
#define printsmbus(x, ...)

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@@ -15,7 +15,7 @@
#ifndef PCI_H
#define PCI_H
#if IS_ENABLED(CONFIG_PCI)
#if CONFIG(PCI)
#include <stdint.h>
#include <stddef.h>

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@@ -32,7 +32,7 @@ u8 *pci_ehci_base_regs(pci_devfn_t dev);
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
#ifndef __PRE_RAM__
#if !IS_ENABLED(CONFIG_USBDEBUG)
#if !CONFIG(USBDEBUG)
#define pci_ehci_read_resources pci_dev_read_resources
#else
/* Relocation of EHCI Debug Port BAR

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@@ -69,7 +69,7 @@ void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
write32(addr, value);
}
#if IS_ENABLED(CONFIG_MMCONF_SUPPORT)
#if CONFIG(MMCONF_SUPPORT)
/* Avoid name collisions as different stages have different signature
* for these functions. The _s_ stands for simple, fundamental IO or

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@@ -54,7 +54,7 @@ static inline int smbus_write_byte(struct device *const dev, u8 addr, u8 val)
int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer);
int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer);
#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS)
#if CONFIG(SMBUS_HAS_AUX_CHANNELS)
void smbus_switch_to_channel(uint8_t channel_number);
uint8_t smbus_get_current_channel(void);
#endif

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@@ -231,7 +231,7 @@ struct elog_event_extended_event {
u32 event_complement;
} __packed;
#if IS_ENABLED(CONFIG_ELOG)
#if CONFIG(ELOG)
/* Eventlog backing storage must be initialized before calling elog_init(). */
extern int elog_init(void);
extern int elog_clear(void);
@@ -264,7 +264,7 @@ static inline int elog_add_extended_event(u8 type, u32 complement) { return 0; }
extern u32 gsmi_exec(u8 command, u32 *param);
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
#if CONFIG(ELOG_BOOT_COUNT)
u32 boot_count_read(void);
#else
static inline u32 boot_count_read(void)

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@@ -16,7 +16,7 @@
#ifndef GIC_H
#define GIC_H
#if IS_ENABLED(CONFIG_GIC)
#if CONFIG(GIC)
/* Initialize the GIC on the currently processor, including GICD and GICC. */
void gic_init(void);

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@@ -177,7 +177,7 @@
INCLUDE "verstage/lib/program.ld"
#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) \
_ = ASSERT(IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE) == 1, \
_ = ASSERT(CONFIG(VBOOT_RETURN_FROM_VERSTAGE) == 1, \
"Must set RETURN_FROM_VERSTAGE to overlap romstage."); \
VERSTAGE(addr, size)
#else

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@@ -6,7 +6,7 @@
* storage can be used. This will benefit machines without CMOS as well as those
* without a battery-backed CMOS (e.g. some laptops).
*/
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
#if CONFIG(USE_OPTION_TABLE)
#include <pc80/mc146818rtc.h>
#else
#include <types.h>

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@@ -1,7 +1,7 @@
#ifndef PC80_MC146818RTC_H
#define PC80_MC146818RTC_H
#if IS_ENABLED(CONFIG_ARCH_X86)
#if CONFIG(ARCH_X86)
#include <arch/io.h>
#include <types.h>
@@ -193,8 +193,8 @@ unsigned int read_option_lowlevel(unsigned int start, unsigned int size,
#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, \
CMOS_VLEN_ ##name, (default))
#if IS_ENABLED(CONFIG_CMOS_POST)
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
#if CONFIG(CMOS_POST)
#if CONFIG(USE_OPTION_TABLE)
# include "option_table.h"
# define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3)
#else
@@ -241,7 +241,7 @@ static inline void cmos_post_init(void)
/* Initialize to zero */
cmos_write(0, CMOS_POST_BANK_0_OFFSET);
cmos_write(0, CMOS_POST_BANK_1_OFFSET);
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
cmos_write32(CMOS_POST_BANK_0_EXTRA, 0);
cmos_write32(CMOS_POST_BANK_1_EXTRA, 0);
#endif
@@ -254,7 +254,7 @@ static inline void cmos_post_log(void) {}
static inline void cmos_post_init(void) {}
#endif /* CONFIG_CMOS_POST */
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
#if CONFIG(USE_OPTION_TABLE)
void sanitize_cmos(void);
#else
static inline void sanitize_cmos(void) {}

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@@ -369,8 +369,8 @@ struct reg_script_bus_entry {
REG_RES_RXW32(bar_, reg_, 0xffffffff, value_)
#if IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \
IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL)
#if CONFIG(SOC_INTEL_BAYTRAIL) || \
CONFIG(SOC_INTEL_FSP_BAYTRAIL)
/*
* IO Sideband Function
*/

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@@ -69,7 +69,7 @@ struct rmodule {
void *relocations;
};
#if IS_ENABLED(CONFIG_RELOCATABLE_MODULES)
#if CONFIG(RELOCATABLE_MODULES)
/* Rmodules have an entry point of named _start. */
#define RMODULE_ENTRY(entry_) \
void _start(void *) __attribute__((alias(STRINGIFY(entry_))))

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@@ -275,7 +275,7 @@
/* x86 specific. Indicates that the current stage is running with cache-as-ram
* enabled from the beginning of the stage in C code. */
#if defined(__PRE_RAM__)
#define ENV_CACHE_AS_RAM IS_ENABLED(CONFIG_CACHE_AS_RAM)
#define ENV_CACHE_AS_RAM CONFIG(CACHE_AS_RAM)
#else
#define ENV_CACHE_AS_RAM 0
#endif

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@@ -1,7 +1,7 @@
#ifndef SMP_ATOMIC_H
#define SMP_ATOMIC_H
#if IS_ENABLED(CONFIG_SMP)
#if CONFIG(SMP)
#include <arch/smp/atomic.h>
#else

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@@ -1,7 +1,7 @@
#ifndef _SMP_NODE_H_
#define _SMP_NODE_H_
#if IS_ENABLED(CONFIG_SMP)
#if CONFIG(SMP)
int boot_cpu(void);
#else
#define boot_cpu(x) 1
@@ -9,7 +9,7 @@ int boot_cpu(void);
static inline int is_smp_boot(void)
{
return IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1;
return CONFIG(SMP) && CONFIG_MAX_CPUS > 1;
}
#endif /* _SMP_NODE_H_ */

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@@ -1,7 +1,7 @@
#ifndef SMP_SPINLOCK_H
#define SMP_SPINLOCK_H
#if IS_ENABLED(CONFIG_SMP)
#if CONFIG(SMP)
#include <arch/smp/spinlock.h>
#else /* !CONFIG_SMP */

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@@ -36,7 +36,7 @@ typedef unsigned int wint_t;
#endif
/* Work around non-writable data segment in execute-in-place romstage on x86. */
#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_ARCH_X86)
#if defined(__PRE_RAM__) && CONFIG(ARCH_X86)
#define MAYBE_STATIC
#else
#define MAYBE_STATIC static

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@@ -21,7 +21,7 @@
#include <timer.h>
#include <arch/cpu.h>
#if IS_ENABLED(CONFIG_COOP_MULTITASKING) && !defined(__SMM__) && !defined(__PRE_RAM__)
#if CONFIG(COOP_MULTITASKING) && !defined(__SMM__) && !defined(__PRE_RAM__)
struct thread {
int id;

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@@ -129,7 +129,7 @@ struct stopwatch {
static inline void stopwatch_init(struct stopwatch *sw)
{
if (IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER))
if (CONFIG(HAVE_MONOTONIC_TIMER))
timer_monotonic_get(&sw->start);
else
sw->start.microseconds = 0;
@@ -153,7 +153,7 @@ static inline void stopwatch_init_msecs_expire(struct stopwatch *sw, long ms)
*/
static inline void stopwatch_tick(struct stopwatch *sw)
{
if (IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER))
if (CONFIG(HAVE_MONOTONIC_TIMER))
timer_monotonic_get(&sw->current);
else
sw->current.microseconds = 0;

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@@ -19,7 +19,7 @@
#include <commonlib/timestamp_serialized.h>
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
#if CONFIG(COLLECT_TIMESTAMPS)
/*
* timestamp_init() needs to be called once for each of these cases:
* 1. __PRE_RAM__ (bootblock, romstage, verstage, etc) and
@@ -59,7 +59,7 @@ uint32_t get_us_since_boot(void);
/**
* Workaround for guard combination above.
*/
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
#if CONFIG(COLLECT_TIMESTAMPS)
/* Implemented by the architecture code */
uint64_t timestamp_get(void);
#else

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@@ -25,7 +25,7 @@
#else /* !__PRE_RAM__ */
#if IS_ENABLED(CONFIG_TRACE) && !defined(__SMM__)
#if CONFIG(TRACE) && !defined(__SMM__)
void __cyg_profile_func_enter(void *, void *)
__attribute__((no_instrument_function));

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@@ -1,7 +1,7 @@
#ifndef WATCHDOG_H
#define WATCHDOG_H
#if IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)
#if CONFIG(USE_WATCHDOG_ON_BOOT)
void watchdog_off(void);
#else
#define watchdog_off() { while (0); }