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coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

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This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julius Werner
2019-03-05 16:53:33 -08:00
committed by Patrick Georgi
parent b3a8cc54db
commit cd49cce7b7
920 changed files with 2285 additions and 2285 deletions
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6
src/northbridge/intel/x4x/raminit.c
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@@ -25,7 +25,7 @@
#include <halt.h>
#include <lib.h>
#include "iomap.h"
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
#else
#include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */
@@ -174,7 +174,7 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
return CB_ERR;
}
if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP))
if (CONFIG(DEBUG_RAM_SETUP))
dram_print_spd_ddr2(&decoded_dimm);
if (!(decoded_dimm.width & (0x08 | 0x10))) {
@@ -383,7 +383,7 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
if (spd_decode_ddr3(&decoded_dimm, raw_spd) != SPD_STATUS_OK)
return CB_ERR;
if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP))
if (CONFIG(DEBUG_RAM_SETUP))
dram_print_spd_ddr3(&decoded_dimm);
/* x4 DIMMs are not supported (true for both ddr2 and ddr3) */