coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/apollolake/acpi.c

@@ -92,10 +92,10 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs)
 	/* Clear out GNVS. */
 	memset(gnvs, 0, sizeof(*gnvs));
 
-	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
+	if (CONFIG(CONSOLE_CBMEM))
 		gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE);
 
-	if (IS_ENABLED(CONFIG_CHROMEOS)) {
+	if (CONFIG(CHROMEOS)) {
 		/* Initialize Verified Boot data */
 		chromeos_init_chromeos_acpi(&gnvs->chromeos);
 		gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
@@ -128,7 +128,7 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs)
 		gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio);
 	}
 
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX))
 		sgx_fill_gnvs(gnvs);
 }
 

src/soc/intel/apollolake/acpi/pci_irqs.asl

@@ -30,7 +30,7 @@ Method(_PRT)
 		Package(){0x000FFFFF, 0, 0, CSE_INT},
 		Package(){0x0011FFFF, 0, 0, ISH_INT},
 		Package(){0x0012FFFF, 0, 0, SATA_INT},
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if CONFIG(SOC_INTEL_GLK)
 		Package(){0x000CFFFF, 0, 0, CNVI_INT},
 		Package(){0x0013FFFF, 0, 0, PIRQF_INT},
 		Package(){0x0013FFFF, 1, 0, PIRQF_INT},

src/soc/intel/apollolake/acpi/southbridge.asl

@@ -45,6 +45,6 @@
 #include <soc/intel/common/acpi/pci_osc.asl>
 
 /* SGX */
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)
 #include <soc/intel/common/acpi/sgx.asl>
 #endif

src/soc/intel/apollolake/acpi/xhci.asl

@@ -34,7 +34,7 @@ Device (XHCI) {
 		/* Root Hub */
 		Name (_ADR, Zero)
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if CONFIG(SOC_INTEL_GLK)
 #include "xhci_glk_ports.asl"
 #else
 #include "xhci_apl_ports.asl"

src/soc/intel/apollolake/bootblock/bootblock.c

@@ -38,7 +38,7 @@
 #include <timestamp.h>
 
 static const struct pad_config tpm_spi_configs[] = {
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if CONFIG(SOC_INTEL_GLK)
 	PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3),	/* FST_SPI_CS2_N */
 #else
 	PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3),	/* FST_SPI_CS2_N */
@@ -95,10 +95,10 @@ void bootblock_soc_early_init(void)
 	pmc_global_reset_enable(0);
 
 	/* Prepare UART for serial console. */
-	if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE))
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 		uart_bootblock_init();
 
-	if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))
+	if (CONFIG(TPM_ON_FAST_SPI))
 		tpm_enable();
 
 	enable_pm_timer_emulation();
@@ -116,7 +116,7 @@ void bootblock_soc_early_init(void)
 	/* Use Nx and paging to prevent the frontend from writing back dirty
 	 * cache-as-ram lines to backing store that doesn't exist when the L1I
 	 * speculatively fetches a line that is sitting in the L1D. */
-	if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)) {
+	if (CONFIG(PAGING_IN_CACHE_AS_RAM)) {
 		paging_set_nxe(1);
 		paging_set_default_pat();
 		paging_enable_for_car("pdpt", "pt");

src/soc/intel/apollolake/chip.c

@@ -124,7 +124,7 @@ const char *soc_acpi_name(const struct device *dev)
 			case 6: return "HS07";
 			case 7: return "HS08";
 			case 8:
-				if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+				if (CONFIG(SOC_INTEL_GLK))
 					return "HS09";
 			}
 			break;
@@ -300,7 +300,7 @@ static void set_power_limits(void)
 	uint32_t tdp, min_power, max_power;
 	uint32_t pl2_val;
 
-	if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) {
+	if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
 		printk(BIOS_INFO, "Skip the RAPL settings.\n");
 		return;
 	}
@@ -527,7 +527,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
 	case PCH_DEVFN_SMBUS:
 		silconfig->SmbusEnable = 0;
 		break;
-#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if !CONFIG(SOC_INTEL_GLK)
 	case SA_DEVFN_IPU:
 		silconfig->IpuEn = 0;
 		break;
@@ -558,7 +558,7 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig)
 static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
 	*cfg, FSP_S_CONFIG *silconfig)
 {
-#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) /* GLK FSP does not have these
+#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these
 					 fields in FspsUpd.h yet */
 	uint8_t port;
 
@@ -597,7 +597,7 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
 static void glk_fsp_silicon_init_params_cb(
 	struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
 {
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if CONFIG(SOC_INTEL_GLK)
 	uint8_t port;
 
 	for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
@@ -730,7 +730,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	/* Disable monitor mwait since it is broken due to a hardware bug
 	 * without a fix. Specific to Apollolake.
 	 */
-	if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+	if (!CONFIG(SOC_INTEL_GLK))
 		silconfig->MonitorMwaitEnable = 0;
 
 	silconfig->SkipMpInit = !chip_get_fsp_mp_init();
@@ -746,7 +746,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
 	/* Bios config lockdown Audio clk and power gate */
 	silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
-	if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+	if (CONFIG(SOC_INTEL_GLK))
 		glk_fsp_silicon_init_params_cb(cfg, silconfig);
 	else
 		apl_fsp_silicon_init_params_cb(cfg, silconfig);
@@ -847,7 +847,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase)
 		 * Override GLK xhci clock gating register(XHCLKGTEN) to
 		 * mitigate usb device suspend and resume failure.
 		 */
-		if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) {
+		if (CONFIG(SOC_INTEL_GLK)) {
 			uint32_t *cfg;
 			const struct resource *res;
 			uint32_t reg;

src/soc/intel/apollolake/cpu.c

@@ -46,7 +46,7 @@
 #include <soc/pm.h>
 
 static const struct reg_script core_msr_script[] = {
-#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if !CONFIG(SOC_INTEL_GLK)
 	/* Enable C-state and IO/MWAIT redirect */
 	REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL,
 		(PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK
@@ -73,7 +73,7 @@ void soc_core_init(struct device *cpu)
 	/* Clear out pending MCEs */
 	/* TODO(adurbin): Some of these banks are core vs package
 			  scope. For now every CPU clears every bank. */
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) ||
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) ||
 	    acpi_get_sleep_type() == ACPI_S5)
 		mca_configure(NULL);
 
@@ -87,20 +87,20 @@ void soc_core_init(struct device *cpu)
 	enable_pm_timer_emulation();
 
 	/* Configure Core PRMRR for SGX. */
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX))
 		prmrr_core_configure();
 
 	/* Set Max Non-Turbo ratio if RAPL is disabled. */
-	if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) {
+	if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
 		cpu_set_p_state_to_max_non_turbo_ratio();
 		cpu_disable_eist();
-	} else if (IS_ENABLED(CONFIG_APL_SET_MIN_CLOCK_RATIO)) {
+	} else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) {
 		cpu_set_p_state_to_min_clock_ratio();
 		cpu_disable_eist();
 	}
 }
 
-#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
+#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
 static void soc_init_core(struct device *cpu)
 {
 	soc_core_init(cpu);
@@ -139,7 +139,7 @@ static struct smm_relocation_attrs relo_attrs;
 /*
  * Do essential initialization tasks before APs can be fired up.
  *
- * IF (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) -
+ * IF (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) -
  * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP,
  * that are set prior to ramstage.
  * Real MTRRs are programmed after resource allocation.
@@ -155,7 +155,7 @@ static struct smm_relocation_attrs relo_attrs;
  */
 static void pre_mp_init(void)
 {
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) {
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) {
 		fsps_load(romstage_handoff_is_resume());
 		return;
 	}
@@ -163,7 +163,7 @@ static void pre_mp_init(void)
 	x86_mtrr_check();
 }
 
-#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
+#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
 static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
 {
 	msr_t msr;
@@ -247,7 +247,7 @@ static void post_mp_init(void)
 {
 	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX))
 		mp_run_on_all_cpus(sgx_configure, NULL, 2000);
 }
 
@@ -270,13 +270,13 @@ void soc_init_cpus(struct bus *cpu_bus)
 
 void apollolake_init_cpus(struct device *dev)
 {
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT))
 		return;
 	soc_init_cpus(dev->link_list);
 
 	/* Temporarily cache the memory-mapped boot media. */
-	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
-		IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
+	if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) &&
+		CONFIG(BOOT_DEVICE_SPI_FLASH))
 		fast_spi_cache_bios_region();
 }
 

src/soc/intel/apollolake/cse.c

@@ -222,7 +222,7 @@ static void dump_cse_version(void *unused)
 	 * Print ME version only if UART debugging is enabled. Else, it takes
 	 * ~0.6 second to talk to ME and get this information.
 	 */
-	if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+	if (!CONFIG(CONSOLE_SERIAL))
 		return;
 
 	msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_GEN;

src/soc/intel/apollolake/graphics.c

@@ -35,14 +35,14 @@ uintptr_t fsp_soc_get_igd_bar(void)
 
 void graphics_soc_init(struct device *const dev)
 {
-	if (IS_ENABLED(CONFIG_RUN_FSP_GOP))
+	if (CONFIG(RUN_FSP_GOP))
 		return;
 
 	uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
 	reg32 |= PCI_COMMAND_MASTER;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
-	if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+	if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
 		if (!acpi_is_wakeup_s3() && display_init_required()) {
 			int lightup_ok;
 			gma_gfxinit(&lightup_ok);

src/soc/intel/apollolake/include/soc/gpio.h

@@ -17,7 +17,7 @@
 #ifndef _SOC_APL_GPIO_H_
 #define _SOC_APL_GPIO_H_
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if CONFIG(SOC_INTEL_GLK)
 #include <soc/gpio_glk.h>
 #else
 #include <soc/gpio_apl.h>

src/soc/intel/apollolake/include/soc/pcr_ids.h

@@ -20,7 +20,7 @@
 /*
  * Port ids.
  */
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if CONFIG(SOC_INTEL_GLK)
 #define PID_GPIO_AUDIO	0xC9
 #define PID_GPIO_SCC	0xC8
 #else

src/soc/intel/apollolake/include/soc/pm.h

@@ -71,7 +71,7 @@
 #define SMI_EOS			1
 #define SMI_GBL			0
 
-#if IS_ENABLED(CONFIG_SOC_ESPI)
+#if CONFIG(SOC_ESPI)
 #define   ESPI_SMI_EN	(1 << SMI_ESPI) /* Valid for GLK with ESPI */
 #else
 #define   ESPI_SMI_EN	0
@@ -190,7 +190,7 @@
 #define  GPE0_DWX_MASK		0xf
 #define GPE0_DW_SHIFT(x)	(4 + 4*(x))
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if CONFIG(SOC_INTEL_GLK)
 #define PMC_GPE_AUDIO_31_0	9
 #define PMC_GPE_N_95_64		8
 #define PMC_GPE_N_63_32		7

src/soc/intel/apollolake/lpc.c

@@ -43,8 +43,8 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
 }
 
 static const struct pad_config lpc_gpios[] = {
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
-#if !IS_ENABLED(CONFIG_SOC_ESPI)
+#if CONFIG(SOC_INTEL_GLK)
+#if !CONFIG(SOC_ESPI)
 	PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1,
 		DISPUPD), /* LPC_CLKOUT0 */
@@ -69,7 +69,7 @@ static const struct pad_config lpc_gpios[] = {
 	 * will keep LPC Controller awake and prevent S0ix entry
 	 */
 	PAD_NC(GPIO_154, NONE),
-#endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */
+#endif /* !CONFIG(SOC_ESPI) */
 #else
 	PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),

src/soc/intel/apollolake/meminit.c

@@ -166,7 +166,7 @@ static const struct fsp_speed_profiles glk_profile = {
 
 static const struct fsp_speed_profiles *get_fsp_profile(void)
 {
-	if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+	if (CONFIG(SOC_INTEL_GLK))
 		return &glk_profile;
 	else
 		return &apl_profile;

src/soc/intel/apollolake/memmap.c

@@ -30,7 +30,7 @@ void *cbmem_top(void)
 	const config_t *config;
 	void *tolum = (void *)sa_get_tseg_base();
 
-	if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+	if (!CONFIG(SOC_INTEL_GLK))
 		return tolum;
 
 	dev = dev_find_slot(0, PCH_DEVFN_LPC);

src/soc/intel/apollolake/romstage.c

@@ -95,7 +95,7 @@ static void soc_early_romstage_init(void)
 	pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
 						P2SB_HPTC_ADDRESS_ENABLE);
 
-	if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))
+	if (CONFIG(DRIVERS_UART_8250IO))
 		lpc_io_setup_comm_a_b();
 }
 
@@ -159,7 +159,7 @@ static bool punit_init(void)
 			PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
 			PUINT_THERMAL_DEVICE_IRQ_LOCK;
 
-	if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) {
+	if (!CONFIG(SOC_INTEL_GLK)) {
 		data = MCHBAR32(0x7818);
 		data &= 0xFFFFE01F;
 		data |= 0x20 | 0x200;
@@ -277,8 +277,8 @@ asmlinkage void car_stage_entry(void)
 
 static void fill_console_params(FSPM_UPD *mupd)
 {
-	if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
-		if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) {
+	if (CONFIG(CONSOLE_SERIAL)) {
+		if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) {
 			mupd->FspmConfig.SerialDebugPortDevice =
 					CONFIG_UART_FOR_CONSOLE;
 			/* use MMIO port type */
@@ -287,7 +287,7 @@ static void fill_console_params(FSPM_UPD *mupd)
 			mupd->FspmConfig.SerialDebugPortStrideSize = 2;
 			/* used only for port type set to external */
 			mupd->FspmConfig.SerialDebugPortAddress = 0;
-		} else if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) {
+		} else if (CONFIG(DRIVERS_UART_8250IO)) {
 			/* use external UART for debug */
 			mupd->FspmConfig.SerialDebugPortDevice = 3;
 			/* use I/O port type */
@@ -320,7 +320,7 @@ static void check_full_retrain(const FSPM_UPD *mupd)
 
 static void soc_memory_init_params(FSPM_UPD *mupd)
 {
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if CONFIG(SOC_INTEL_GLK)
 	/* Only for GLK */
 	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
 	assert(dev != NULL);
@@ -351,7 +351,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
 
 static void parse_devicetree_setting(FSPM_UPD *m_upd)
 {
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if CONFIG(SOC_INTEL_GLK)
 	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK);
 	if (!dev)
 		return;
@@ -368,7 +368,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	fill_console_params(mupd);
 
-	if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+	if (CONFIG(SOC_INTEL_GLK))
 		soc_memory_init_params(mupd);
 
 	mainboard_memory_init_params(mupd);
@@ -385,7 +385,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	 * as designed.
 	 */
 	mupd->FspmConfig.SkipCseRbp =
-		IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED);
+		CONFIG(BOOT_DEVICE_MEMORY_MAPPED);
 
 	/*
 	 * Converged Security Engine (CSE) has secure storage functionality.
@@ -407,7 +407,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) {
 		/* Assume leaking is ok. */
-		assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+		assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
 		mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev);
 	}
 

src/soc/intel/apollolake/smihandler.c

@@ -50,7 +50,7 @@ const smi_handler_t southbridge_smi[32] = {
 	[GPIO_SMI_STS] = smihandler_southbridge_gpi,
 	[TCO_SMI_STS] = smihandler_southbridge_tco,
 	[PERIODIC_SMI_STS] = smihandler_southbridge_periodic,
-#if IS_ENABLED(CONFIG_SOC_ESPI)
+#if CONFIG(SOC_ESPI)
 	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
 #endif
 };

src/soc/intel/apollolake/uart.c

@@ -28,7 +28,7 @@
 
 /* UART pad configuration. Support RXD and TXD for now. */
 const struct uart_gpio_pad_config uart_gpio_pads[] = {
-#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#if CONFIG(SOC_INTEL_GLK)
 	{
 		.console_index = 0,
 		.gpios = {

src/soc/intel/baytrail/acpi.c

@@ -83,15 +83,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 	/* Top of Low Memory (start of resource allocation) */
 	gnvs->tolm = nc_read_top_of_low_memory();
 
-#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
+#if CONFIG(CONSOLE_CBMEM)
 	/* Update the mem console pointer. */
 	gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 #endif
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
 	/* Initialize Verified Boot data */
 	chromeos_init_chromeos_acpi(&(gnvs->chromeos));
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
 	gnvs->chromeos.vbt2 = google_ec_running_ro() ?
 		ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
 #endif

src/soc/intel/baytrail/include/soc/pmc.h

@@ -281,7 +281,7 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
 void southcluster_log_state(void);
 #else
 static inline void southcluster_log_state(void) {}

src/soc/intel/baytrail/include/soc/ramstage.h

@@ -25,7 +25,7 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);
 void baytrail_init_cpus(struct device *dev);
 void set_max_freq(void);
 void southcluster_enable_dev(struct device *dev);
-#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)
+#if CONFIG(HAVE_REFCODE_BLOB)
 void baytrail_run_reference_code(void);
 #else
 static inline void baytrail_run_reference_code(void) {}

src/soc/intel/baytrail/include/soc/romstage.h

@@ -39,7 +39,7 @@ void punit_init(void);
 void set_max_freq(void);
 int early_spi_read_wpsr(u8 *sr);
 
-#if IS_ENABLED(CONFIG_ENABLE_BUILTIN_COM1)
+#if CONFIG(ENABLE_BUILTIN_COM1)
 void byt_config_com1_and_enable(void);
 #else
 static inline void byt_config_com1_and_enable(void) { }

src/soc/intel/baytrail/northcluster.c

@@ -131,7 +131,7 @@ static void nc_read_resources(struct device *dev)
 	reserved_ram_resource(dev, index++, (0xc0000 >> 10),
 	                      (0x100000 - 0xc0000) >> 10);
 
-	if (IS_ENABLED(CONFIG_CHROMEOS))
+	if (CONFIG(CHROMEOS))
 		chromeos_reserve_ram_oops(dev, index++);
 }
 

src/soc/intel/baytrail/romstage/raminit.c

@@ -112,7 +112,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 	mp->version = MRC_PARAMS_VER;
 	mp->console_out = &send_to_console;
 	mp->prev_sleep_state = prev_sleep_state;
-	mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT);
+	mp->rmt_enabled = CONFIG(MRC_RMT);
 
 	/* Default to 2GiB IO hole. */
 	if (!mp->io_hole_mb)
@@ -124,7 +124,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 		mp->saved_data_size = region_device_sz(&rdev);
 		mp->saved_data = rdev_mmap_full(&rdev);
 		/* Assume boot device is memory mapped. */
-		assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+		assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
 	} else if (prev_sleep_state == ACPI_S3) {
 		/* If waking from S3 and no cache then. */
 		printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
@@ -157,7 +157,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 	if (prev_sleep_state != ACPI_S3) {
 		cbmem_initialize_empty();
 	} else if (cbmem_initialize()) {
-	#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+	#if CONFIG(HAVE_ACPI_RESUME)
 		printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
 		/* Failed S3 resume, reset to come up cleanly */
 		system_reset();

src/soc/intel/baytrail/romstage/romstage.c

@@ -22,7 +22,7 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #endif
 #include <elog.h>
@@ -193,7 +193,7 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps)
 	if (ps->pm1_sts & WAK_STS) {
 		switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
 		case ACPI_S3:
-			if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+			if (CONFIG(HAVE_ACPI_RESUME))
 				prev_sleep_state = ACPI_S3;
 			break;
 		case ACPI_S5:
@@ -224,7 +224,7 @@ void romstage_common(struct romstage_params *params)
 
 	printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
 
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+#if CONFIG(ELOG_BOOT_COUNT)
 	if (prev_sleep_state != ACPI_S3)
 		boot_count_increment();
 #endif

src/soc/intel/baytrail/smihandler.c

@@ -113,7 +113,7 @@ static void southbridge_smi_sleep(void)
 	/* Do any mainboard sleep handling */
 	mainboard_smi_sleep(slp_typ);
 
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 	/* Log S3, S4, and S5 entry */
 	if (slp_typ >= ACPI_S3)
 		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -209,7 +209,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
 	return NULL;
 }
 
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 static void southbridge_smi_gsmi(void)
 {
 	u32 *ret, *param;
@@ -242,7 +242,7 @@ static void finalize(void)
 	}
 	finalize_done = 1;
 
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
 	/* Re-init SPI driver to handle locked BAR */
 	spi_init();
 #endif
@@ -347,7 +347,7 @@ static void southbridge_smi_apmc(void)
 			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
 		}
 		break;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 	case APM_CNT_ELOG_GSMI:
 		southbridge_smi_gsmi();
 		break;
@@ -373,7 +373,7 @@ static void southbridge_smi_pm1(void)
 	 */
 	if (pm1_sts & PWRBTN_STS) {
 		// power button pressed
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 		elog_add_event(ELOG_TYPE_POWER_BUTTON);
 #endif
 		disable_pm1_control(-1UL);

src/soc/intel/baytrail/spi.c

@@ -134,7 +134,7 @@ enum {
 	SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =	3
 };
 
-#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
+#if CONFIG(DEBUG_SPI_FLASH)
 
 static u8 readb_(const void *addr)
 {

src/soc/intel/braswell/acpi.c

@@ -89,15 +89,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 	/* Top of Low Memory (start of resource allocation) */
 	gnvs->tolm = nc_read_top_of_low_memory();
 
-#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
+#if CONFIG(CONSOLE_CBMEM)
 	/* Update the mem console pointer. */
 	gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 #endif
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
 	/* Initialize Verified Boot data */
 	chromeos_init_chromeos_acpi(&(gnvs->chromeos));
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
 	gnvs->chromeos.vbt2 = google_ec_running_ro() ?
 		ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
 #endif
@@ -492,12 +492,12 @@ unsigned long southcluster_write_acpi_tables(struct device *device,
 	acpi_header_t *ssdt2;
 	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 
-	if (!IS_ENABLED(CONFIG_DISABLE_HPET)) {
+	if (!CONFIG(DISABLE_HPET)) {
 		current = acpi_write_hpet(device, current, rsdp);
 		current = acpi_align_current(current);
 	}
 
-	if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) {
+	if (CONFIG(INTEL_GMA_ADD_VBT)) {
 		igd_opregion_t *opregion;
 
 		printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
@@ -543,7 +543,7 @@ void southcluster_inject_dsdt(struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* Fill in the Wifi Region id */
-		if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN))
+		if (CONFIG(HAVE_REGULATORY_DOMAIN))
 			gnvs->cid1 = wifi_regulatory_domain();
 		else
 			gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;

src/soc/intel/braswell/acpi/lpc.asl

@@ -48,7 +48,7 @@ Device (LPCB)
 		})
 	}
 
-#if !IS_ENABLED(CONFIG_DISABLE_HPET)
+#if !CONFIG(DISABLE_HPET)
 	Device (HPET)
 	{
 		Name (_HID, EISAID("PNP0103"))

src/soc/intel/braswell/gfx.c

@@ -67,7 +67,7 @@ static void gfx_init(struct device *dev)
 	printk(BIOS_SPEW, "%s/%s (%s)\n",
 			__FILE__, __func__, dev_name(dev));
 
-	if (!IS_ENABLED(CONFIG_RUN_FSP_GOP)) {
+	if (!CONFIG(RUN_FSP_GOP)) {
 		/* Pre VBIOS Init */
 		gfx_pre_vbios_init(dev);
 

src/soc/intel/braswell/include/soc/pm.h

@@ -242,7 +242,7 @@ void enable_gpe(uint32_t mask);
 void disable_gpe(uint32_t mask);
 void disable_all_gpe(void);
 
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
 void southcluster_log_state(void);
 #else
 static inline void southcluster_log_state(void) {}

src/soc/intel/braswell/memmap.c

@@ -37,7 +37,7 @@ void smm_region(void **start, size_t *size)
 size_t mmap_region_granularity(void)
 {
 	/* Align to TSEG size when SMM is in use, and 8MiB by default */
-	return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? smm_region_size()
+	return CONFIG(HAVE_SMI_HANDLER) ? smm_region_size()
 		: 8 << 20;
 }
 

src/soc/intel/braswell/northcluster.c

@@ -165,7 +165,7 @@ static void nc_read_resources(struct device *dev)
 	size_k = RES_IN_KIB(0x00100000);
 	mmio_resource(dev, index++, base_k, size_k);
 
-	if (IS_ENABLED(CONFIG_CHROMEOS))
+	if (CONFIG(CHROMEOS))
 		chromeos_reserve_ram_oops(dev, index++);
 }
 

src/soc/intel/braswell/romstage/romstage.c

@@ -161,7 +161,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
 	if (ps->pm1_sts & WAK_STS) {
 		switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
 		case ACPI_S3:
-			if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+			if (CONFIG(HAVE_ACPI_RESUME))
 				prev_sleep_state = ACPI_S3;
 			break;
 		case ACPI_S5:
@@ -229,7 +229,7 @@ void soc_memory_init_params(struct romstage_params *params,
 
 	config = dev->chip_info;
 	printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
-	upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
+	upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ?
 		config->PcdMrcInitTsegSize : 0;
 	upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize;
 	upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1;

src/soc/intel/braswell/smihandler.c

@@ -153,7 +153,7 @@ static void southbridge_smi_sleep(void)
 	/* Do any mainboard sleep handling */
 	mainboard_smi_sleep(slp_typ);
 
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 	/* Log S3, S4, and S5 entry */
 	if (slp_typ >= ACPI_S3)
 		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -259,7 +259,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
 	return NULL;
 }
 
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 static void southbridge_smi_gsmi(void)
 {
 	u32 *ret, *param;
@@ -292,7 +292,7 @@ static void finalize(void)
 	}
 	finalize_done = 1;
 
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
 	/* Re-init SPI driver to handle locked BAR */
 	spi_init();
 #endif
@@ -345,7 +345,7 @@ static void southbridge_smi_apmc(void)
 			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
 		}
 		break;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 	case APM_CNT_ELOG_GSMI:
 		southbridge_smi_gsmi();
 		break;
@@ -368,7 +368,7 @@ static void southbridge_smi_pm1(void)
 	 */
 	if (pm1_sts & PWRBTN_STS) {
 		/* power button pressed */
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 		elog_add_event(ELOG_TYPE_POWER_BUTTON);
 #endif
 		disable_pm1_control(-1UL);

src/soc/intel/braswell/spi.c

@@ -119,7 +119,7 @@ enum {
 	SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =	3
 };
 
-#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
+#if CONFIG(DEBUG_SPI_FLASH)
 
 static u8 readb_(void *addr)
 {

src/soc/intel/broadwell/acpi.c

@@ -169,15 +169,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 	/* CPU core count */
 	gnvs->pcnt = dev_count_cpu();
 
-#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
+#if CONFIG(CONSOLE_CBMEM)
 	/* Update the mem console pointer. */
 	gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 #endif
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
 	/* Initialize Verified Boot data */
 	chromeos_init_chromeos_acpi(&(gnvs->chromeos));
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
 	gnvs->chromeos.vbt2 = google_ec_running_ro() ?
 		ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
 #endif

src/soc/intel/broadwell/chip.c

@@ -30,7 +30,7 @@ static struct device_operations pci_domain_ops = {
 	.read_resources    = &pci_domain_read_resources,
 	.set_resources     = &pci_domain_set_resources,
 	.scan_bus          = &pci_domain_scan_bus,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	.write_acpi_tables = &northbridge_write_acpi_tables,
 #endif
 };

src/soc/intel/broadwell/finalize.c

@@ -56,7 +56,7 @@ const struct reg_script system_agent_finalize_script[] = {
 };
 
 const struct reg_script pch_finalize_script[] = {
-#if !IS_ENABLED(CONFIG_SPI_CONSOLE)
+#if !CONFIG(SPI_CONSOLE)
 	/* Set SPI opcode menu */
 	REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP,
 			 SPI_OPPREFIX),

src/soc/intel/broadwell/igd.c

@@ -512,7 +512,7 @@ static void igd_init(struct device *dev)
 
 	/* Wait for any configured pre-graphics delay */
 	if (!acpi_is_wakeup_s3()) {
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
 		if (display_init_required() || vboot_wants_oprom())
 			mdelay(CONFIG_PRE_GRAPHICS_DELAY);
 #else

src/soc/intel/broadwell/include/soc/ramstage.h

@@ -23,7 +23,7 @@ void broadwell_init_pre_device(void *chip_info);
 void broadwell_init_cpus(struct device *dev);
 void broadwell_pch_enable_dev(struct device *dev);
 
-#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)
+#if CONFIG(HAVE_REFCODE_BLOB)
 void broadwell_run_reference_code(void);
 #else
 static inline void broadwell_run_reference_code(void) { }

src/soc/intel/broadwell/lpc.c

@@ -219,7 +219,7 @@ static const struct reg_script pch_misc_init_script[] = {
 	REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)),
 	/* Setup SERIRQ, enable continuous mode */
 	REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
-#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
+#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
 	REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
 #endif
 	REG_SCRIPT_END
@@ -429,7 +429,7 @@ static void pch_cg_init(struct device *dev)
 
 static void pch_set_acpi_mode(void)
 {
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
 	if (!acpi_is_wakeup_s3()) {
 		printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
 		outb(APM_CNT_ACPI_DISABLE, APM_CNT);
@@ -621,7 +621,7 @@ static unsigned long broadwell_write_acpi_tables(struct device *device,
 						 unsigned long current,
 						 struct acpi_rsdp *rsdp)
 {
-	if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE))
+	if (CONFIG(INTEL_PCH_UART_CONSOLE))
 		current = acpi_write_dbg2_pci_uart(rsdp, current,
 			(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1) ?
 				PCH_DEV_UART1 : PCH_DEV_UART0,

src/soc/intel/broadwell/me.c

@@ -40,7 +40,7 @@
 #include <soc/rcba.h>
 #include <soc/intel/broadwell/chip.h>
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 #endif
@@ -58,7 +58,7 @@ static const char *me_bios_path_values[] = {
 /* MMIO base address for MEI interface */
 static u8 *mei_base_address;
 
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
 static void mei_dump(void *ptr, int dword, int offset, const char *type)
 {
 	struct mei_csr *csr;
@@ -483,7 +483,7 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name)
 	       vers_name->hotfix_version, vers_name->build_version);
 }
 
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
 static inline void print_cap(const char *name, int state)
 {
 	printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n",
@@ -703,7 +703,7 @@ static me_bios_path intel_me_path(struct device *dev)
 		path = ME_ERROR_BIOS_PATH;
 	}
 
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
 	if (path != ME_NORMAL_BIOS_PATH) {
 		struct elog_event_data_me_extended data = {
 			.current_working_state = hfs.working_state,
@@ -792,7 +792,7 @@ static int intel_me_extend_valid(struct device *dev)
 	}
 	printk(BIOS_DEBUG, "\n");
 
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
 	/* Save hash in NVS for the OS to verify */
 	chromeos_set_me_hash(extend, count);
 #endif
@@ -804,7 +804,7 @@ static void intel_me_print_mbp(me_bios_payload *mbp_data)
 {
 	me_print_fw_version(mbp_data->fw_version_name);
 
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
 	me_print_fwcaps(mbp_data->fw_capabilities);
 #endif
 
@@ -912,7 +912,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
 	}
 
 	/* Dump out the MBP contents. */
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
 	printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
 	       mbp->header.num_entries, mbp->header.mbp_size);
 	for (i = 0; i < mbp->header.mbp_size - 1; i++)

src/soc/intel/broadwell/pcie.c

@@ -555,7 +555,7 @@ static void pch_pcie_early(struct device *dev)
 	pci_update_config8(dev, 0xf5, 0x0f, 0);
 
 	/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
-	if (IS_ENABLED(CONFIG_PCIEXP_AER))
+	if (CONFIG(PCIEXP_AER))
 		pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
 			(1 << 29) | 0x10001);
 	else
@@ -563,7 +563,7 @@ static void pch_pcie_early(struct device *dev)
 			(1 << 29));
 
 	/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
-	if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE))
+	if (CONFIG(PCIEXP_L1_SUB_STATE))
 		pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
 	else
 		pci_update_config32(dev, 0x200, ~0xfffff, 0);

src/soc/intel/broadwell/romstage/power_state.c

@@ -57,7 +57,7 @@ static int prev_sleep_state(struct chipset_power_state *ps)
 	if (ps->pm1_sts & WAK_STS) {
 		switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
 		case ACPI_S3:
-			if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+			if (CONFIG(HAVE_ACPI_RESUME))
 				prev_sleep_state = ACPI_S3;
 			break;
 		case ACPI_S5:

src/soc/intel/broadwell/romstage/raminit.c

@@ -24,7 +24,7 @@
 #include <memory_info.h>
 #include <mrc_cache.h>
 #include <string.h>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #endif
@@ -57,7 +57,7 @@ void raminit(struct pei_data *pei_data)
 		pei_data->saved_data_size = region_device_sz(&rdev);
 		pei_data->saved_data = rdev_mmap_full(&rdev);
 		/* Assume boot device is memory mapped. */
-		assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+		assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
 	} else if (pei_data->boot_mode == ACPI_S3) {
 		/* Waking from S3 and no cache. */
 		printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
@@ -104,7 +104,7 @@ void raminit(struct pei_data *pei_data)
 	if (pei_data->boot_mode != ACPI_S3) {
 		cbmem_initialize_empty();
 	} else if (cbmem_initialize()) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
 		printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
 		/* Failed S3 resume, reset to come up cleanly */
 		system_reset();

src/soc/intel/broadwell/romstage/romstage.c

@@ -123,7 +123,7 @@ void romstage_common(struct romstage_params *params)
 
 	params->pei_data->boot_mode = params->power_state->prev_sleep_state;
 
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+#if CONFIG(ELOG_BOOT_COUNT)
 	if (params->power_state->prev_sleep_state != ACPI_S3)
 		boot_count_increment();
 #endif

src/soc/intel/broadwell/serialio.c

@@ -41,7 +41,7 @@ static void serialio_enable_d3hot(struct resource *res)
 
 static int serialio_uart_is_debug(struct device *dev)
 {
-#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)
+#if CONFIG(INTEL_PCH_UART_CONSOLE)
 	switch (dev->path.pci.devfn) {
 	case PCH_DEVFN_UART0: /* UART0 */
 		return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0);
@@ -278,7 +278,7 @@ static void serialio_set_resources(struct device *dev)
 {
 	pci_dev_set_resources(dev);
 
-#if IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)
+#if CONFIG(INTEL_PCH_UART_CONSOLE)
 	/* Update UART base address if used for debug */
 	if (serialio_uart_is_debug(dev)) {
 		struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);

src/soc/intel/broadwell/smihandler.c

@@ -178,7 +178,7 @@ static void southbridge_smi_sleep(void)
 	/* USB sleep preparations */
 	usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ);
 
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 	/* Log S3, S4, and S5 entry */
 	if (slp_typ >= ACPI_S3)
 		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -292,7 +292,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
 	return NULL;
 }
 
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 static void southbridge_smi_gsmi(void)
 {
 	u32 *ret, *param;
@@ -325,7 +325,7 @@ static void finalize(void)
 	}
 	finalize_done = 1;
 
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
 	/* Re-init SPI driver to handle locked BAR */
 	spi_init();
 #endif
@@ -371,7 +371,7 @@ static void southbridge_smi_apmc(void)
 			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
 		}
 		break;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 	case APM_CNT_ELOG_GSMI:
 		southbridge_smi_gsmi();
 		break;
@@ -390,7 +390,7 @@ static void southbridge_smi_pm1(void)
 	 */
 	if (pm1_sts & PWRBTN_STS) {
 		/* power button pressed */
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
 		elog_add_event(ELOG_TYPE_POWER_BUTTON);
 #endif
 		disable_pm1_control(-1UL);

src/soc/intel/broadwell/spi.c

@@ -133,7 +133,7 @@ enum {
 	SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =	3
 };
 
-#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
+#if CONFIG(DEBUG_SPI_FLASH)
 
 static u8 readb_(const void *addr)
 {

src/soc/intel/broadwell/systemagent.c

@@ -384,7 +384,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 	reserved_ram_resource(dev, index++, (0xc0000 >> 10),
 				(0x100000 - 0xc0000) >> 10);
 
-	if (IS_ENABLED(CONFIG_CHROMEOS))
+	if (CONFIG(CHROMEOS))
 		chromeos_reserve_ram_oops(dev, index++);
 
 	*resource_cnt = index;

src/soc/intel/cannonlake/acpi.c

@@ -204,14 +204,14 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs)
 	/* CPU core count */
 	gnvs->pcnt = dev_count_cpu();
 
-	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
+	if (CONFIG(CONSOLE_CBMEM))
 	/* Update the mem console pointer. */
 	gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
 
-	if (IS_ENABLED(CONFIG_CHROMEOS)) {
+	if (CONFIG(CHROMEOS)) {
 		/* Initialize Verified Boot data */
 		chromeos_init_chromeos_acpi(&(gnvs->chromeos));
-		if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+		if (CONFIG(EC_GOOGLE_CHROMEEC)) {
 			gnvs->chromeos.vbt2 = google_ec_running_ro() ?
 				ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
 		} else

src/soc/intel/cannonlake/acpi/scs.asl

@@ -112,7 +112,7 @@ Scope (\_SB.PCI0) {
 			And (PMCR, 0xFFFC, PMCR)
 			Store (PMCR, ^TEMP)
 
-#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)
+#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)
 			/* Change pad mode to Native */
 			GPMO(SD_PWR_EN_PIN, 0x1)
 #endif
@@ -126,7 +126,7 @@ Scope (\_SB.PCI0) {
 			Or (PMCR, 0x0003, PMCR)
 			Store (PMCR, ^TEMP)
 
-#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)
+#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)
 			/* Change pad mode to GPIO control */
 			GPMO(SD_PWR_EN_PIN, 0x0)
 

src/soc/intel/cannonlake/acpi/southbridge.asl

@@ -30,7 +30,7 @@
 #include "scs.asl"
 
 /* GPIO controller */
-#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
 #include "gpio_cnp_h.asl"
 #else
 #include "gpio.asl"

src/soc/intel/cannonlake/bootblock/bootblock.c

@@ -20,7 +20,7 @@
 #include <soc/iomap.h>
 #include <soc/pch.h>
 
-#if IS_ENABLED(CONFIG_FSP_CAR)
+#if CONFIG(FSP_CAR)
 #include <FsptUpd.h>
 
 const FSPT_UPD temp_ram_init_params = {
@@ -53,7 +53,7 @@ void bootblock_soc_early_init(void)
 	bootblock_pch_early_init();
 	bootblock_cpu_init();
 	pch_early_iorange_init();
-	if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE))
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 		uart_bootblock_init();
 }
 

src/soc/intel/cannonlake/bootblock/cpu.c

@@ -21,7 +21,7 @@
 void bootblock_cpu_init(void)
 {
 	/* Temporarily cache the memory-mapped boot media. */
-	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
-		IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
+	if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) &&
+		CONFIG(BOOT_DEVICE_SPI_FLASH))
 		fast_spi_cache_bios_region();
 }

src/soc/intel/cannonlake/bootblock/pch.c

@@ -162,7 +162,7 @@ void pch_early_iorange_init(void)
 		LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
 
 	/* IO Decode Range */
-	if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))
+	if (CONFIG(DRIVERS_UART_8250IO))
 		lpc_io_setup_comm_a_b();
 
 	/* IO Decode Enable */

src/soc/intel/cannonlake/chip.c

@@ -29,7 +29,7 @@
 #include <soc/ramstage.h>
 #include <string.h>
 
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {
 	if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -195,7 +195,7 @@ static struct device_operations pci_domain_ops = {
 	.read_resources   = &pci_domain_read_resources,
 	.set_resources    = &pci_domain_set_resources,
 	.scan_bus         = &pci_domain_scan_bus,
-	#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+	#if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_name        = &soc_acpi_name,
 	#endif
 };

src/soc/intel/cannonlake/chip.h

@@ -30,7 +30,7 @@
 #include <soc/serialio.h>
 #include <soc/usb.h>
 #include <soc/vr_config.h>
-#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
 #include <soc/gpio_defs_cnp_h.h>
 #else
 #include <soc/gpio_defs.h>
@@ -107,7 +107,7 @@ struct soc_intel_cannonlake_config {
 	enum {
 		SaGv_Disabled,
 		SaGv_FixedLow,
-#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE)
+#if !CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
 		SaGv_FixedMid,
 #endif
 		SaGv_FixedHigh,

src/soc/intel/cannonlake/cnl_memcfg_init.c

@@ -90,7 +90,7 @@ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg,
 		die("spd.bin not found or incorrect index\n");
 	spd_data_len = region_device_sz(&spd_rdev);
 	/* Memory leak is ok since we have memory mapped boot media */
-	assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
 	spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
 	meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr);
 }

src/soc/intel/cannonlake/cpu.c

@@ -497,7 +497,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 	 * have this check, where CNL CPU die is not based on KBL CPU
 	 * so skip this check for CNL.
 	 */
-	if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE))
+	if (!CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE))
 		return 0;
 
 	/*

src/soc/intel/cannonlake/fsp_params.c

@@ -213,7 +213,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	} else {
 		params->ScsSdCardEnabled = dev->enabled;
 		params->SdCardPowerEnableActiveHigh =
-			IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
+			CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
 	}
 
 	dev = dev_find_slot(0, PCH_DEVFN_UFS);

src/soc/intel/cannonlake/graphics.c

@@ -54,7 +54,7 @@ void graphics_soc_init(struct device *dev)
 	 * In case of non-FSP solution, SoC need to select VGA_ROM_RUN
 	 * Kconfig to perform GFX initialization through VGA OpRom.
 	 */
-	if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT))
+	if (CONFIG(INTEL_GMA_ADD_VBT))
 		return;
 
 	/* IGD needs to Bus Master */

src/soc/intel/cannonlake/include/soc/gpio.h

@@ -16,7 +16,7 @@
 #ifndef _SOC_CANNONLAKE_GPIO_H_
 #define _SOC_CANNONLAKE_GPIO_H_
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
 #include <soc/gpio_defs_cnp_h.h>
 #define CROS_GPIO_DEVICE_NAME	"INT3450:00"
 #else

src/soc/intel/cannonlake/include/soc/pmc.h

@@ -116,7 +116,7 @@
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
 #define PMC_GPP_A			0x0
 #define PMC_GPP_B			0x1
 #define PMC_GPP_C			0x2

src/soc/intel/cannonlake/include/soc/smm.h

@@ -50,7 +50,7 @@ struct smm_relocation_params {
 /* Mainboard handler for eSPI SMIs */
 void mainboard_smi_espi_handler(void);
 
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
 void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase);
 void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,

src/soc/intel/cannonlake/lpc.c

@@ -227,7 +227,7 @@ void lpc_soc_init(struct device *dev)
 	lpc_enable_pci_clk_cntl();
 
 	/* Set LPC Serial IRQ mode */
-	if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
+	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
 		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
 	else
 		lpc_set_serirq_mode(SERIRQ_QUIET);

src/soc/intel/cannonlake/memmap.c

@@ -147,7 +147,7 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base,
 	traditional_mem_base -= sa_get_tseg_size();
 
 	/* Get DPR size */
-	if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
+	if (CONFIG(SA_ENABLE_DPR))
 		traditional_mem_base -= sa_get_dpr_size();
 
 	/* Traditional Area Size */

src/soc/intel/cannonlake/romstage/fsp_params.c

@@ -34,7 +34,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
 	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
 	m_cfg->SaGv = config->SaGv;
-	if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H))
+	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
 		m_cfg->UserBd = BOARD_TYPE_DESKTOP;
 	else
 		m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
@@ -53,7 +53,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 		m_cfg->VmxEnable = 0;
 	else
 		m_cfg->VmxEnable = config->VmxEnable;
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE)
+#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
 	m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
 #endif
 

src/soc/intel/cannonlake/smihandler.c

@@ -93,7 +93,7 @@ void smihandler_soc_at_finalize(void)
 
 void smihandler_soc_check_illegal_access(uint32_t tco_sts)
 {
-	if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+	if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
 			&& fast_spi_wpd_status()))
 		return;
 

src/soc/intel/common/acpi/acpi_debug.asl

@@ -13,11 +13,11 @@
  * GNU General Public License for more details.
  */
 
-#if IS_ENABLED(CONFIG_ACPI_CONSOLE)
+#if CONFIG(ACPI_CONSOLE)
 
 #include <soc/iomap.h>
 
-Name (UFLG, IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+Name (UFLG, CONFIG(CONSOLE_SERIAL))
 
 Method (LURT, 1, Serialized)
 {
@@ -57,7 +57,7 @@ Method (APRT, 1, Serialized)
 	}
 	Store (INDX, LENG) /* Length of the String */
 
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)
+#if CONFIG(DRIVERS_UART_8250MEM_32)
 	OperationRegion (UBAR, SystemMemory,
 				UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE), 24)
 	Field (UBAR, AnyAcc, NoLock, Preserve)

src/soc/intel/common/acpi/platform.asl

@@ -34,7 +34,7 @@ Method (_PTS, 1)
 {
 	Store (POST_OS_ENTER_PTS, DBG0)
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK)
+#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK)
 	/* Call EC _PTS handler */
 	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
 #endif
@@ -46,7 +46,7 @@ Method (_WAK, 1)
 {
 	Store (POST_OS_ENTER_WAKE, DBG0)
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK)
+#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK)
 	/* Call EC _WAK handler */
 	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
 #endif

src/soc/intel/common/block/acpi/acpi.c

@@ -180,7 +180,7 @@ uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
 	return generic_pm1_en;
 }
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
+#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
 /*
  * Save wake source information for calculating ACPI _SWS values
  *
@@ -452,7 +452,7 @@ void generate_cpu_entries(struct device *device)
 	acpigen_write_processor_cnot(cores_per_package);
 }
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
+#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
 /* Save wake source data for ACPI _SWS methods in NVS */
 static void acpi_save_wake_source(void *unused)
 {

src/soc/intel/common/block/cpu/car/cache_as_ram.S

@@ -167,11 +167,11 @@ clear_var_mtrr:
 	invd
 	mov	%eax, %cr0
 
-#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
+#if CONFIG(INTEL_CAR_NEM)
 	jmp car_nem
-#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
+#elif CONFIG(INTEL_CAR_CQOS)
 	jmp car_cqos
-#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
+#elif CONFIG(INTEL_CAR_NEM_ENHANCED)
 	jmp car_nem_enhanced
 #else
 	jmp	.halt_forever /* In case nothing has selected */
@@ -221,7 +221,7 @@ fixed_mtrr_list:
 	.word	MTRR_FIX_4K_F8000
 fixed_mtrr_list_size = . - fixed_mtrr_list
 
-#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
+#if CONFIG(INTEL_CAR_NEM)
 .global car_nem
 car_nem:
 	/* Disable cache eviction (setup stage) */
@@ -252,7 +252,7 @@ car_nem:
 
 	jmp car_init_done
 
-#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
+#elif CONFIG(INTEL_CAR_CQOS)
 .global car_cqos
 car_cqos:
 	/*
@@ -356,7 +356,7 @@ car_cqos:
 
 	jmp car_init_done
 
-#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
+#elif CONFIG(INTEL_CAR_NEM_ENHANCED)
 .global car_nem_enhanced
 car_nem_enhanced:
 	/* Disable cache eviction (setup stage) */

src/soc/intel/common/block/cpu/car/exit_car.S

@@ -23,7 +23,7 @@
 .global chipset_teardown_car
 chipset_teardown_car:
 
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
 	/*
 	 * Since Page table is located in CAR, disable paging before CAR
 	 * teardown. Also clear CR3 and CR4.PAE.
@@ -50,7 +50,7 @@ chipset_teardown_car:
 	and	$(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
 	wrmsr
 
-#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
+#if CONFIG(INTEL_CAR_NEM)
 .global car_nem_teardown
 car_nem_teardown:
 
@@ -65,7 +65,7 @@ car_nem_teardown:
 	and	$(~(1 << 0)), %eax
 	wrmsr
 
-#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
+#elif CONFIG(INTEL_CAR_CQOS)
 .global car_cqos_teardown
 car_cqos_teardown:
 
@@ -86,7 +86,7 @@ car_cqos_teardown:
 	and	$~IA32_PQR_ASSOC_MASK, %edx
 	wrmsr
 
-#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
+#elif CONFIG(INTEL_CAR_NEM_ENHANCED)
 .global car_nem_enhanced_teardown
 car_nem_enhanced_teardown:
 

src/soc/intel/common/block/fast_spi/fast_spi.c

@@ -157,7 +157,7 @@ void fast_spi_lock_bar(void)
 	void *spibar = fast_spi_get_bar();
 	uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN;
 
-	if (IS_ENABLED(CONFIG_FAST_SPI_DISABLE_WRITE_STATUS))
+	if (CONFIG(FAST_SPI_DISABLE_WRITE_STATUS))
 		hsfs |= SPIBAR_HSFSTS_WRSDIS;
 
 	write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);

src/soc/intel/common/block/gpio/gpio.c

@@ -35,7 +35,7 @@
 	PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK |			\
 	PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK)
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
 #define PAD_DW1_MASK	(PAD_CFG1_IOSTERM_MASK |			\
 			PAD_CFG1_PULL_MASK |				\
 			PAD_CFG1_TOL_MASK |				\
@@ -190,7 +190,7 @@ static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port,
 	if (ENV_SMM)
 		return;
 
-	if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG))
+	if (!CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG))
 		return;
 
 	int irq;
@@ -276,7 +276,7 @@ static void gpio_configure_pad(const struct pad_config *cfg)
 		/* Patch GPIO settings for SoC specifically */
 		soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
 
-		if (IS_ENABLED(CONFIG_DEBUG_GPIO))
+		if (CONFIG(DEBUG_GPIO))
 			printk(BIOS_DEBUG,
 			"gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
 			" : 0x%08x]\n",
@@ -411,7 +411,7 @@ uint16_t gpio_acpi_pin(gpio_t gpio_num)
 	const struct pad_community *comm;
 	size_t group, pin;
 
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES))
 		return relative_pad_in_comm(gpio_get_community(gpio_num),
 					    gpio_num);
 
@@ -489,7 +489,7 @@ void gpi_clear_get_smi_status(struct gpi_status *sts)
 		comm++;
 	}
 
-	if (IS_ENABLED(CONFIG_DEBUG_SMI))
+	if (CONFIG(DEBUG_SMI))
 		print_gpi_status(sts);
 
 }
@@ -560,7 +560,7 @@ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d)
 			MISCCFG_GPE0_DW1_MASK |
 			MISCCFG_GPE0_DW0_MASK);
 
-	if (IS_ENABLED(CONFIG_DEBUG_GPIO))
+	if (CONFIG(DEBUG_GPIO))
 		printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n",
 			misccfg_mask, misccfg_value);
 	comm = soc_gpio_get_community(&gpio_communities);

src/soc/intel/common/block/gspi/gspi.c

@@ -355,7 +355,7 @@ static uint32_t gspi_csctrl_state_v1(uint32_t pol, enum cs_assert cs_assert)
 
 static uint32_t gspi_csctrl_state(uint32_t pol, enum cs_assert cs_assert)
 {
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2))
 		return gspi_csctrl_state_v2(pol, cs_assert);
 
 	return gspi_csctrl_state_v1(pol, cs_assert);
@@ -379,7 +379,7 @@ static uint32_t gspi_csctrl_polarity_v1(enum spi_polarity active_pol)
 
 static uint32_t gspi_csctrl_polarity(enum spi_polarity active_pol)
 {
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2))
 		return gspi_csctrl_polarity_v2(active_pol);
 
 	return gspi_csctrl_polarity_v1(active_pol);

src/soc/intel/common/block/hda/hda.c

@@ -23,7 +23,7 @@
 #include <soc/intel/common/hda_verb.h>
 #include <soc/ramstage.h>
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)
 static void codecs_init(uint8_t *base, u32 codec_mask)
 {
 	int i;
@@ -65,7 +65,7 @@ static struct device_operations hda_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)
 	.init			= hda_init,
 #endif
 	.ops_pci		= &pci_dev_ops_pci,

src/soc/intel/common/block/include/intelblocks/gpio_defs.h

@@ -76,7 +76,7 @@
 #define  PAD_CFG1_PULL_UP_20K		(0xc << 10)
 #define  PAD_CFG1_PULL_UP_667		(0xd << 10)
 #define  PAD_CFG1_PULL_NATIVE		(0xf << 10)
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
 /* Tx enabled driving last value driven, Rx enabled */
 #define PAD_CFG1_IOSSTATE_TxLASTRxE	(0x0 << 14)
 /* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
@@ -125,7 +125,7 @@
 #define PAD_CFG2_DEBOUNCE_MASK		0x1f
 
 /* voltage tolerance  0=3.3V default 1=1.8V tolerant */
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
 #define PAD_CFG1_TOL_MASK		(0x1 << 25)
 #define  PAD_CFG1_TOL_1V8		(0x1 << 25)
 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */
@@ -134,7 +134,7 @@
 #define PAD_RESET(value)	PAD_CFG0_LOGICAL_RESET_##value
 #define PAD_PULL(value)		PAD_CFG1_PULL_##value
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
 #define PAD_IOSSTATE(value)	PAD_CFG1_IOSSTATE_##value
 #define PAD_IOSTERM(value)	PAD_CFG1_IOSTERM_##value
 #else
@@ -147,7 +147,7 @@
 				PAD_CFG0_TRIG_##trig | \
 				PAD_CFG0_RX_POL_##inv)
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
 #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv)  \
 				(PAD_CFG0_ROUTE_##route1 | \
 				PAD_CFG0_ROUTE_##route2 | \
@@ -180,7 +180,7 @@
 	_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
 		PAD_IOSSTATE(TxLASTRxE))
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
 /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S
     Not applicable to all SOCs. Refer EDS
  */
@@ -269,7 +269,7 @@
  */
 #define PAD_NC(pad, pull)	PAD_CFG_GPI(pad, pull, DEEP)
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS)
 
 #define PAD_CFG_GPI_APIC(pad, pull, rst) \
 	_PAD_CFG_STRUCT(pad,		\
@@ -384,7 +384,7 @@
 		PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
 		PAD_IOSSTATE(TxDRxE))
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
 #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \
 	_PAD_CFG_STRUCT(pad,						\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \

src/soc/intel/common/block/lpc/lpc_lib.c

@@ -240,7 +240,7 @@ void lpc_io_setup_comm_a_b(void)
 	uint16_t com_enable = LPC_IOE_COMA_EN;
 
 	/* ComB Range 2F8h-2FFh [6:4] */
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) {
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) {
 		com_ranges |= LPC_IOD_COMB_RANGE;
 		com_enable |= LPC_IOE_COMB_EN;
 	}

src/soc/intel/common/block/pcie/pcie.c

@@ -46,7 +46,7 @@ static void pch_pcie_init(struct device *dev)
 	/* disable parity error response, enable ISA */
 	pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2);
 
-	if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) {
+	if (CONFIG(PCIE_DEBUG_INFO)) {
 		printk(BIOS_SPEW, "    MBL    = 0x%08x\n",
 				pci_read_config32(dev, PCI_MEMORY_BASE));
 		printk(BIOS_SPEW, "    PMBL   = 0x%08x\n",

src/soc/intel/common/block/pcr/pcr.c

@@ -25,7 +25,7 @@
 #error "PCR_BASE_ADDRESS need to be non-zero!"
 #endif
 
-#if !IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0)
+#if !CONFIG(PCR_COMMON_IOSF_1_0)
 
 #define PCR_SBI_CMD_TIMEOUT	10 /* 10ms */
 
@@ -76,7 +76,7 @@ static void *__pcr_reg_address(uint8_t pid, uint16_t offset)
 
 void *pcr_reg_address(uint8_t pid, uint16_t offset)
 {
-	if (IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0))
+	if (CONFIG(PCR_COMMON_IOSF_1_0))
 		assert(IS_ALIGNED(offset, sizeof(uint32_t)));
 
 	return __pcr_reg_address(pid, offset);
@@ -91,7 +91,7 @@ void *pcr_reg_address(uint8_t pid, uint16_t offset)
  */
 static inline void check_pcr_offset_align(uint16_t offset, size_t size)
 {
-	const size_t align = IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0) ?
+	const size_t align = CONFIG(PCR_COMMON_IOSF_1_0) ?
 					sizeof(uint32_t) : size;
 
 	assert(IS_ALIGNED(offset, align));
@@ -219,7 +219,7 @@ void pcr_or8(uint8_t pid, uint16_t offset, uint8_t ordata)
 	pcr_write8(pid, offset, data8);
 }
 
-#if !IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0)
+#if !CONFIG(PCR_COMMON_IOSF_1_0)
 
 #ifdef __SIMPLE_DEVICE__
 static int pcr_wait_for_completion(pci_devfn_t dev)

src/soc/intel/common/block/pmc/pmc.c

@@ -66,7 +66,7 @@ static void pch_pmc_add_io_resources(struct device *dev,
 			cfg->abase_addr, cfg->abase_size,
 			 IORESOURCE_IO | IORESOURCE_ASSIGNED |
 			 IORESOURCE_FIXED);
-	if (IS_ENABLED(CONFIG_PMC_INVALID_READ_AFTER_WRITE)) {
+	if (CONFIG(PMC_INVALID_READ_AFTER_WRITE)) {
 		/*
 		 * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've
 		 * observed cases where the BAR reads back as 0, but the IO
@@ -105,7 +105,7 @@ static void pch_pmc_read_resources(struct device *dev)
 
 void pmc_set_acpi_mode(void)
 {
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
+	if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
 		printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
 		outb(APM_CNT_ACPI_DISABLE, APM_CNT);
 		printk(BIOS_DEBUG, "done.\n");

src/soc/intel/common/block/pmc/pmclib.c

@@ -384,7 +384,7 @@ static int pmc_prev_sleep_state(const struct chipset_power_state *ps)
 	if (ps->pm1_sts & WAK_STS) {
 		switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
 		case ACPI_S3:
-			if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+			if (CONFIG(HAVE_ACPI_RESUME))
 				prev_sleep_state = ACPI_S3;
 			break;
 		case ACPI_S5:
@@ -432,7 +432,7 @@ int pmc_fill_power_state(struct chipset_power_state *ps)
 	return ps->prev_sleep_state;
 }
 
-#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK)
+#if CONFIG(PMC_GLOBAL_RESET_ENABLE_LOCK)
 /*
  * If possible, lock 0xcf9. Once the register is locked, it can't be changed.
  * This lock is reset on cold boot, hard reset, soft reset and Sx.

src/soc/intel/common/block/rtc/rtc.c

@@ -53,7 +53,7 @@ void rtc_conf_set_bios_interface_lockdown(void)
 					PCR_RTC_CONF_BILD);
 }
 
-#if IS_ENABLED(CONFIG_INTEL_HAS_TOP_SWAP)
+#if CONFIG(INTEL_HAS_TOP_SWAP)
 void configure_rtc_buc_top_swap(enum ts_config ts_state)
 {
 	pcr_rmw32(PID_RTC, PCR_RTC_BUC, ~PCR_RTC_BUC_TOP_SWAP, ts_state);

src/soc/intel/common/block/sata/sata.c

@@ -52,7 +52,7 @@ static void sata_final(struct device *dev)
 	/* Read Ports Implemented (GHC_PI) */
 	port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED);
 
-	if (IS_ENABLED(CONFIG_SOC_AHCI_PORT_IMPLEMENTED_INVERT))
+	if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT))
 		port_impl = ~port_impl;
 
 	port_impl &= 0x07; /* bit 0-2 */

src/soc/intel/common/block/scs/sd.c

@@ -19,7 +19,7 @@
 #include <device/pci_ids.h>
 #include <intelblocks/sd.h>
 
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 static void sd_fill_ssdt(struct device *dev)
 {
 	const char *path;
@@ -59,7 +59,7 @@ static struct device_operations dev_ops = {
 	.read_resources			= pci_dev_read_resources,
 	.set_resources			= pci_dev_set_resources,
 	.enable_resources		= pci_dev_enable_resources,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_fill_ssdt_generator	= sd_fill_ssdt,
 #endif
 	.ops_pci			= &pci_dev_ops_pci,

src/soc/intel/common/block/smbus/tco.c

@@ -133,7 +133,7 @@ static void tco_enable_bar(void)
  */
 void tco_configure(void)
 {
-	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS))
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS))
 		tco_enable_bar();
 
 	tco_timer_disable();

src/soc/intel/common/block/smm/smihandler.c

@@ -192,7 +192,7 @@ void smihandler_southbridge_sleep(
 	mainboard_smi_sleep(slp_typ);
 
 	/* Log S3, S4, and S5 entry */
-	if (slp_typ >= ACPI_S3 && IS_ENABLED(CONFIG_ELOG_GSMI))
+	if (slp_typ >= ACPI_S3 && CONFIG(ELOG_GSMI))
 		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
 
 	/* Clear pending GPE events */
@@ -324,7 +324,7 @@ static void finalize(void)
 	}
 	finalize_done = 1;
 
-	if (IS_ENABLED(CONFIG_SPI_FLASH_SMM))
+	if (CONFIG(SPI_FLASH_SMM))
 		/* Re-init SPI driver to handle locked BAR */
 		fast_spi_init();
 
@@ -361,13 +361,13 @@ void smihandler_southbridge_apmc(
 		break;
 	case APM_CNT_ACPI_DISABLE:
 		pmc_disable_pm1_control(SCI_EN);
-		if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
+		if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
 			pmc_enable_smi(ESPI_SMI_EN);
 		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
 	case APM_CNT_ACPI_ENABLE:
 		pmc_enable_pm1_control(SCI_EN);
-		if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
+		if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
 			pmc_disable_smi(ESPI_SMI_EN);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
@@ -387,11 +387,11 @@ void smihandler_southbridge_apmc(
 		}
 		break;
 	case APM_CNT_ELOG_GSMI:
-		if (IS_ENABLED(CONFIG_ELOG_GSMI))
+		if (CONFIG(ELOG_GSMI))
 			southbridge_smi_gsmi(save_state_ops);
 		break;
 	case APM_CNT_SMMSTORE:
-		if (IS_ENABLED(CONFIG_SMMSTORE))
+		if (CONFIG(SMMSTORE))
 			southbridge_smi_store(save_state_ops);
 		break;
 	case APM_CNT_FINALIZE:
@@ -414,7 +414,7 @@ void smihandler_southbridge_pm1(
 	 */
 	if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) {
 		/* power button pressed */
-		if (IS_ENABLED(CONFIG_ELOG_GSMI))
+		if (CONFIG(ELOG_GSMI))
 			elog_add_event(ELOG_TYPE_POWER_BUTTON);
 		pmc_disable_pm1_control(-1UL);
 		pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));

src/soc/intel/common/block/smm/smm.c

@@ -95,7 +95,7 @@ void smm_region_info(void **start, size_t *size)
 	*size = sa_get_tseg_size();
 }
 
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)
 static void smm_disable_espi(void *dest)
 {
 	pmc_disable_smi(ESPI_SMI_EN);

src/soc/intel/common/block/spi/spi.c

@@ -26,7 +26,7 @@
 
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 	{ .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
-#if !ENV_SMM && IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI)
+#if !ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI)
 	{ .ctrlr = &gspi_ctrlr, .bus_start = 1,
 	  .bus_end =  1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
 #endif

src/soc/intel/common/block/systemagent/systemagent.c

@@ -160,7 +160,7 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
 	uintptr_t top_of_ram;
 	int index = *resource_count;
 
-	if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
+	if (CONFIG(SA_ENABLE_DPR))
 		dpr_size = sa_get_dpr_size();
 
 	/* Get SoC reserve memory size as per user selection */
@@ -270,7 +270,7 @@ static void systemagent_read_resources(struct device *dev)
 	soc_add_fixed_mmio_resources(dev, &index);
 	/* Calculate and add DRAM resources. */
 	sa_add_dram_resources(dev, &index);
-	if (IS_ENABLED(CONFIG_SA_ENABLE_IMR))
+	if (CONFIG(SA_ENABLE_IMR))
 		/* Add the isolated memory ranges (IMRs). */
 		sa_add_imr_resources(dev, &index);
 }
@@ -292,7 +292,7 @@ static struct device_operations systemagent_ops = {
 	.enable_resources = pci_dev_enable_resources,
 	.init             = soc_systemagent_init,
 	.ops_pci          = &pci_dev_ops_pci,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	.write_acpi_tables = sa_write_acpi_tables,
 #endif
 };

src/soc/intel/common/block/uart/uart.c

@@ -45,7 +45,7 @@ static void uart_lpss_init(uintptr_t baseaddr)
 			CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL);
 }
 
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
+#if CONFIG(DRIVERS_UART_8250MEM)
 uintptr_t uart_platform_base(int idx)
 {
 	/* return Base address for UART console index */
@@ -92,7 +92,7 @@ struct device *uart_get_device(void)
 	 * config option is not selected.
 	 * By default return NULL in this case to avoid compilation errors.
 	 */
-	if (!IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE))
+	if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 		return NULL;
 
 	int console_index = uart_get_valid_index();
@@ -141,7 +141,7 @@ void uart_bootblock_init(void)
 	uart_common_init(uart_get_device(),
 		UART_BASE(CONFIG_UART_FOR_CONSOLE));
 
-	if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
+	if (!CONFIG(DRIVERS_UART_8250MEM_32))
 		/* Put UART in byte access mode for 16550 compatibility */
 		soc_uart_set_legacy_mode();
 
@@ -156,7 +156,7 @@ static void uart_read_resources(struct device *dev)
 	pci_dev_read_resources(dev);
 
 	/* Set the configured UART base address for the debug port */
-	if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE) &&
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) &&
 	    uart_is_debug_controller(dev)) {
 		struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
 		/* Need to set the base and size for the resource allocator. */
@@ -204,7 +204,7 @@ static bool uart_controller_needs_init(struct device *dev)
 	 * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing
 	 * controller here.
 	 */
-	if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+	if (CONFIG(CONSOLE_SERIAL))
 		return false;
 
 	/* If this device does not correspond to debug port, then skip. */

src/soc/intel/common/block/xhci/xhci.c

@@ -29,7 +29,7 @@ static struct device_operations usb_xhci_ops = {
 	.init			= soc_xhci_init,
 	.ops_pci		= &pci_dev_ops_pci,
 	.scan_bus		= scan_usb_bus,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_name		= soc_acpi_name,
 #endif
 };

src/soc/intel/common/pch/lockdown/lockdown.c

@@ -58,7 +58,7 @@ static void dmi_lockdown_cfg(void)
 
 static void fast_spi_lockdown_cfg(int chipset_lockdown)
 {
-	if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI))
+	if (!CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI))
 		return;
 
 	/* Set FAST_SPI opcode menu */

src/soc/intel/common/vbt.c

@@ -22,7 +22,7 @@
 
 void *vbt_get(void)
 {
-	if (!IS_ENABLED(CONFIG_RUN_FSP_GOP))
+	if (!CONFIG(RUN_FSP_GOP))
 		return NULL;
 
 	/* Normal mode and S3 resume path PEIM GFX init is not needed.

src/soc/intel/denverton_ns/acpi.c

@@ -83,7 +83,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 	/* Top of Low Memory (start of resource allocation) */
 	gnvs->tolm = top_of_32bit_ram();
 
-#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
+#if CONFIG(CONSOLE_CBMEM)
 	/* Update the mem console pointer. */
 	gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 #endif
@@ -140,7 +140,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 	u16 pmbase = get_pmbase();
 
 	/* System Management */
-	if (!IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+	if (!CONFIG(HAVE_SMI_HANDLER)) {
 		fadt->smi_cmd = 0x00;
 		fadt->acpi_enable = 0x00;
 		fadt->acpi_disable = 0x00;

src/soc/intel/denverton_ns/bootblock/bootblock.c

@@ -58,13 +58,13 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 void bootblock_soc_early_init(void)
 {
 
-#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+#if (CONFIG(CONSOLE_SERIAL))
 	early_uart_init();
 #endif
 };
 
 void bootblock_soc_init(void)
 {
-	if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE))
+	if (CONFIG(BOOTBLOCK_CONSOLE))
 		printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
 };

src/soc/intel/denverton_ns/bootblock/uart.c

@@ -41,7 +41,7 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func,
 	reg16 = pci_read_config16(uart_dev, PCI_BASE_ADDRESS_0) | mmio_base;
 	pci_write_config16(uart_dev, PCI_BASE_ADDRESS_0, reg16);
 
-#if (IS_ENABLED(CONFIG_NON_LEGACY_UART_MODE))
+#if (CONFIG(NON_LEGACY_UART_MODE))
 	/* Decode MMIO at MEMBA (BAR1) */
 	pci_write_config32(uart_dev, PCI_BASE_ADDRESS_1,
 			   CONFIG_CONSOLE_UART_BASE_ADDRESS +
@@ -53,12 +53,12 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func,
 	 */
 	pci_write_config16(uart_dev, PCI_COMMAND,
 			   pci_read_config16(uart_dev, PCI_COMMAND) |
-#if (IS_ENABLED(CONFIG_NON_LEGACY_UART_MODE))
+#if (CONFIG(NON_LEGACY_UART_MODE))
 			   PCI_COMMAND_MEMORY |
 #endif
 				   PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 
-#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_230400))
+#if (CONFIG(CONSOLE_SERIAL_230400))
 	/* Change the highest speed to 230400 */
 	uint32_t *psr_reg =
 		(uint32_t *)(CONFIG_CONSOLE_UART_BASE_ADDRESS +