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coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

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This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julius Werner
2019-03-05 16:53:33 -08:00
committed by Patrick Georgi
parent b3a8cc54db
commit cd49cce7b7
920 changed files with 2285 additions and 2285 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/apollolake/acpi.c
View File

@@ -92,10 +92,10 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs)
/* Clear out GNVS. */
memset(gnvs, 0, sizeof(*gnvs));
if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
if (CONFIG(CONSOLE_CBMEM))
gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE);
if (IS_ENABLED(CONFIG_CHROMEOS)) {
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&gnvs->chromeos);
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
@@ -128,7 +128,7 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs)
gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio);
}
if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX))
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX))
sgx_fill_gnvs(gnvs);
}

2
src/soc/intel/apollolake/acpi/pci_irqs.asl
View File

@@ -30,7 +30,7 @@ Method(_PRT)
Package(){0x000FFFFF, 0, 0, CSE_INT},
Package(){0x0011FFFF, 0, 0, ISH_INT},
Package(){0x0012FFFF, 0, 0, SATA_INT},
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GLK)
Package(){0x000CFFFF, 0, 0, CNVI_INT},
Package(){0x0013FFFF, 0, 0, PIRQF_INT},
Package(){0x0013FFFF, 1, 0, PIRQF_INT},

2
src/soc/intel/apollolake/acpi/southbridge.asl
View File

@@ -45,6 +45,6 @@
#include <soc/intel/common/acpi/pci_osc.asl>
/* SGX */
#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)
#include <soc/intel/common/acpi/sgx.asl>
#endif

2
src/soc/intel/apollolake/acpi/xhci.asl
View File

@@ -34,7 +34,7 @@ Device (XHCI) {
/* Root Hub */
Name (_ADR, Zero)
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GLK)
#include "xhci_glk_ports.asl"
#else
#include "xhci_apl_ports.asl"

8
src/soc/intel/apollolake/bootblock/bootblock.c
View File

@@ -38,7 +38,7 @@
#include <timestamp.h>
static const struct pad_config tpm_spi_configs[] = {
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GLK)
PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
#else
PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
@@ -95,10 +95,10 @@ void bootblock_soc_early_init(void)
pmc_global_reset_enable(0);
/* Prepare UART for serial console. */
if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE))
if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
uart_bootblock_init();
if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))
if (CONFIG(TPM_ON_FAST_SPI))
tpm_enable();
enable_pm_timer_emulation();
@@ -116,7 +116,7 @@ void bootblock_soc_early_init(void)
/* Use Nx and paging to prevent the frontend from writing back dirty
* cache-as-ram lines to backing store that doesn't exist when the L1I
* speculatively fetches a line that is sitting in the L1D. */
if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)) {
if (CONFIG(PAGING_IN_CACHE_AS_RAM)) {
paging_set_nxe(1);
paging_set_default_pat();
paging_enable_for_car("pdpt", "pt");

16
src/soc/intel/apollolake/chip.c
View File

@@ -124,7 +124,7 @@ const char *soc_acpi_name(const struct device *dev)
case 6: return "HS07";
case 7: return "HS08";
case 8:
if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
if (CONFIG(SOC_INTEL_GLK))
return "HS09";
}
break;
@@ -300,7 +300,7 @@ static void set_power_limits(void)
uint32_t tdp, min_power, max_power;
uint32_t pl2_val;
if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) {
if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
printk(BIOS_INFO, "Skip the RAPL settings.\n");
return;
}
@@ -527,7 +527,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
case PCH_DEVFN_SMBUS:
silconfig->SmbusEnable = 0;
break;
#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if !CONFIG(SOC_INTEL_GLK)
case SA_DEVFN_IPU:
silconfig->IpuEn = 0;
break;
@@ -558,7 +558,7 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig)
static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
*cfg, FSP_S_CONFIG *silconfig)
{
#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) /* GLK FSP does not have these
#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these
fields in FspsUpd.h yet */
uint8_t port;
@@ -597,7 +597,7 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
static void glk_fsp_silicon_init_params_cb(
struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
{
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GLK)
uint8_t port;
for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
@@ -730,7 +730,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* Disable monitor mwait since it is broken due to a hardware bug
* without a fix. Specific to Apollolake.
*/
if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
if (!CONFIG(SOC_INTEL_GLK))
silconfig->MonitorMwaitEnable = 0;
silconfig->SkipMpInit = !chip_get_fsp_mp_init();
@@ -746,7 +746,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
/* Bios config lockdown Audio clk and power gate */
silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
if (CONFIG(SOC_INTEL_GLK))
glk_fsp_silicon_init_params_cb(cfg, silconfig);
else
apl_fsp_silicon_init_params_cb(cfg, silconfig);
@@ -847,7 +847,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase)
* Override GLK xhci clock gating register(XHCLKGTEN) to
* mitigate usb device suspend and resume failure.
*/
if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) {
if (CONFIG(SOC_INTEL_GLK)) {
uint32_t *cfg;
const struct resource *res;
uint32_t reg;

26
src/soc/intel/apollolake/cpu.c
View File

@@ -46,7 +46,7 @@
#include <soc/pm.h>
static const struct reg_script core_msr_script[] = {
#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if !CONFIG(SOC_INTEL_GLK)
/* Enable C-state and IO/MWAIT redirect */
REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL,
(PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK
@@ -73,7 +73,7 @@ void soc_core_init(struct device *cpu)
/* Clear out pending MCEs */
/* TODO(adurbin): Some of these banks are core vs package
scope. For now every CPU clears every bank. */
if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) ||
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) ||
acpi_get_sleep_type() == ACPI_S5)
mca_configure(NULL);
@@ -87,20 +87,20 @@ void soc_core_init(struct device *cpu)
enable_pm_timer_emulation();
/* Configure Core PRMRR for SGX. */
if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX))
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX))
prmrr_core_configure();
/* Set Max Non-Turbo ratio if RAPL is disabled. */
if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) {
if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
cpu_set_p_state_to_max_non_turbo_ratio();
cpu_disable_eist();
} else if (IS_ENABLED(CONFIG_APL_SET_MIN_CLOCK_RATIO)) {
} else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) {
cpu_set_p_state_to_min_clock_ratio();
cpu_disable_eist();
}
}
#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
static void soc_init_core(struct device *cpu)
{
soc_core_init(cpu);
@@ -139,7 +139,7 @@ static struct smm_relocation_attrs relo_attrs;
/*
* Do essential initialization tasks before APs can be fired up.
*
* IF (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) -
* IF (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) -
* Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP,
* that are set prior to ramstage.
* Real MTRRs are programmed after resource allocation.
@@ -155,7 +155,7 @@ static struct smm_relocation_attrs relo_attrs;
*/
static void pre_mp_init(void)
{
if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) {
if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) {
fsps_load(romstage_handoff_is_resume());
return;
}
@@ -163,7 +163,7 @@ static void pre_mp_init(void)
x86_mtrr_check();
}
#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
{
msr_t msr;
@@ -247,7 +247,7 @@ static void post_mp_init(void)
{
smm_southbridge_enable(PWRBTN_EN | GBL_EN);
if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX))
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX))
mp_run_on_all_cpus(sgx_configure, NULL, 2000);
}
@@ -270,13 +270,13 @@ void soc_init_cpus(struct bus *cpu_bus)
void apollolake_init_cpus(struct device *dev)
{
if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT))
if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT))
return;
soc_init_cpus(dev->link_list);
/* Temporarily cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) &&
CONFIG(BOOT_DEVICE_SPI_FLASH))
fast_spi_cache_bios_region();
}

2
src/soc/intel/apollolake/cse.c
View File

@@ -222,7 +222,7 @@ static void dump_cse_version(void *unused)
* Print ME version only if UART debugging is enabled. Else, it takes
* ~0.6 second to talk to ME and get this information.
*/
if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL))
if (!CONFIG(CONSOLE_SERIAL))
return;
msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_GEN;

4
src/soc/intel/apollolake/graphics.c
View File

@@ -35,14 +35,14 @@ uintptr_t fsp_soc_get_igd_bar(void)
void graphics_soc_init(struct device *const dev)
{
if (IS_ENABLED(CONFIG_RUN_FSP_GOP))
if (CONFIG(RUN_FSP_GOP))
return;
uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
if (!acpi_is_wakeup_s3() && display_init_required()) {
int lightup_ok;
gma_gfxinit(&lightup_ok);

2
src/soc/intel/apollolake/include/soc/gpio.h
View File

@@ -17,7 +17,7 @@
#ifndef _SOC_APL_GPIO_H_
#define _SOC_APL_GPIO_H_
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GLK)
#include <soc/gpio_glk.h>
#else
#include <soc/gpio_apl.h>

2
src/soc/intel/apollolake/include/soc/pcr_ids.h
View File

@@ -20,7 +20,7 @@
/*
* Port ids.
*/
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GLK)
#define PID_GPIO_AUDIO 0xC9
#define PID_GPIO_SCC 0xC8
#else

4
src/soc/intel/apollolake/include/soc/pm.h
View File

@@ -71,7 +71,7 @@
#define SMI_EOS 1
#define SMI_GBL 0
#if IS_ENABLED(CONFIG_SOC_ESPI)
#if CONFIG(SOC_ESPI)
#define ESPI_SMI_EN (1 << SMI_ESPI) /* Valid for GLK with ESPI */
#else
#define ESPI_SMI_EN 0
@@ -190,7 +190,7 @@
#define GPE0_DWX_MASK 0xf
#define GPE0_DW_SHIFT(x) (4 + 4*(x))
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GLK)
#define PMC_GPE_AUDIO_31_0 9
#define PMC_GPE_N_95_64 8
#define PMC_GPE_N_63_32 7

6
src/soc/intel/apollolake/lpc.c
View File

@@ -43,8 +43,8 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
}
static const struct pad_config lpc_gpios[] = {
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if !IS_ENABLED(CONFIG_SOC_ESPI)
#if CONFIG(SOC_INTEL_GLK)
#if !CONFIG(SOC_ESPI)
PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1,
DISPUPD), /* LPC_CLKOUT0 */
@@ -69,7 +69,7 @@ static const struct pad_config lpc_gpios[] = {
* will keep LPC Controller awake and prevent S0ix entry
*/
PAD_NC(GPIO_154, NONE),
#endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */
#endif /* !CONFIG(SOC_ESPI) */
#else
PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),

2
src/soc/intel/apollolake/meminit.c
View File

@@ -166,7 +166,7 @@ static const struct fsp_speed_profiles glk_profile = {
static const struct fsp_speed_profiles *get_fsp_profile(void)
{
if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
if (CONFIG(SOC_INTEL_GLK))
return &glk_profile;
else
return &apl_profile;

2
src/soc/intel/apollolake/memmap.c
View File

@@ -30,7 +30,7 @@ void *cbmem_top(void)
const config_t *config;
void *tolum = (void *)sa_get_tseg_base();
if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
if (!CONFIG(SOC_INTEL_GLK))
return tolum;
dev = dev_find_slot(0, PCH_DEVFN_LPC);

20
src/soc/intel/apollolake/romstage.c
View File

@@ -95,7 +95,7 @@ static void soc_early_romstage_init(void)
pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
P2SB_HPTC_ADDRESS_ENABLE);
if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))
if (CONFIG(DRIVERS_UART_8250IO))
lpc_io_setup_comm_a_b();
}
@@ -159,7 +159,7 @@ static bool punit_init(void)
PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
PUINT_THERMAL_DEVICE_IRQ_LOCK;
if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) {
if (!CONFIG(SOC_INTEL_GLK)) {
data = MCHBAR32(0x7818);
data &= 0xFFFFE01F;
data |= 0x20 | 0x200;
@@ -277,8 +277,8 @@ asmlinkage void car_stage_entry(void)
static void fill_console_params(FSPM_UPD *mupd)
{
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) {
if (CONFIG(CONSOLE_SERIAL)) {
if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) {
mupd->FspmConfig.SerialDebugPortDevice =
CONFIG_UART_FOR_CONSOLE;
/* use MMIO port type */
@@ -287,7 +287,7 @@ static void fill_console_params(FSPM_UPD *mupd)
mupd->FspmConfig.SerialDebugPortStrideSize = 2;
/* used only for port type set to external */
mupd->FspmConfig.SerialDebugPortAddress = 0;
} else if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) {
} else if (CONFIG(DRIVERS_UART_8250IO)) {
/* use external UART for debug */
mupd->FspmConfig.SerialDebugPortDevice = 3;
/* use I/O port type */
@@ -320,7 +320,7 @@ static void check_full_retrain(const FSPM_UPD *mupd)
static void soc_memory_init_params(FSPM_UPD *mupd)
{
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GLK)
/* Only for GLK */
const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
assert(dev != NULL);
@@ -351,7 +351,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
static void parse_devicetree_setting(FSPM_UPD *m_upd)
{
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GLK)
DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK);
if (!dev)
return;
@@ -368,7 +368,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
fill_console_params(mupd);
if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
if (CONFIG(SOC_INTEL_GLK))
soc_memory_init_params(mupd);
mainboard_memory_init_params(mupd);
@@ -385,7 +385,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
* as designed.
*/
mupd->FspmConfig.SkipCseRbp =
IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED);
CONFIG(BOOT_DEVICE_MEMORY_MAPPED);
/*
* Converged Security Engine (CSE) has secure storage functionality.
@@ -407,7 +407,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) {
/* Assume leaking is ok. */
assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev);
}

2
src/soc/intel/apollolake/smihandler.c
View File

@@ -50,7 +50,7 @@ const smi_handler_t southbridge_smi[32] = {
[GPIO_SMI_STS] = smihandler_southbridge_gpi,
[TCO_SMI_STS] = smihandler_southbridge_tco,
[PERIODIC_SMI_STS] = smihandler_southbridge_periodic,
#if IS_ENABLED(CONFIG_SOC_ESPI)
#if CONFIG(SOC_ESPI)
[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
#endif
};

2
src/soc/intel/apollolake/uart.c
View File

@@ -28,7 +28,7 @@
/* UART pad configuration. Support RXD and TXD for now. */
const struct uart_gpio_pad_config uart_gpio_pads[] = {
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GLK)
{
.console_index = 0,
.gpios = {