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coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

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This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julius Werner
2019-03-05 16:53:33 -08:00
committed by Patrick Georgi
parent b3a8cc54db
commit cd49cce7b7
920 changed files with 2285 additions and 2285 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/southbridge/amd/agesa/hudson/acpi/fch.asl
View File

@@ -58,7 +58,7 @@ Device(SDCN) {
Name(_ADR, 0x00140007)
} /* end SDCN */
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
/* 0:14.4 - PCI slot 1, 2, 3 */
Device(PIBR) {
@@ -146,7 +146,7 @@ Method(_CRS, 0) {
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
#if CONFIG(HUDSON_IMC_FWM)
#include "acpi/AmdImc.asl" /* Hudson IMC function */
#endif
@@ -175,8 +175,8 @@ Method(_INI, 0) {
/* Determine the OS we're running on */
OSFL()
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
#if CONFIG(HUDSON_IMC_FWM)
#if CONFIG(ACPI_ENABLE_THERMAL_ZONE)
ITZE() /* enable IMC Fan Control*/
#endif
#endif

4
src/southbridge/amd/agesa/hudson/acpi/usb.asl
View File

@@ -50,7 +50,7 @@ Device(UOH6) {
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
/* 0:14.5 - OHCI */
Device(UEH1) {
Name(_ADR, 0x00140005)
@@ -64,7 +64,7 @@ Device(XHC0) {
Name(_PRW, Package() {0x0B, 4})
} /* end XHC0 */
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
/* 0:10.1 - XHCI 1*/
Device(XHC1) {
Name(_ADR, 0x00100001)

8
src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
View File

@@ -21,9 +21,9 @@
* into the FCH PCI_INTR 0xC00/0xC01 interrupt
* routing table
*/
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define FCH_INT_TABLE_SIZE 0x54
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#define FCH_INT_TABLE_SIZE 0x42
#endif
@@ -51,7 +51,7 @@
#define PIRQ_FC 0x14 /* FC */
#define PIRQ_GEC 0x15 /* GEC */
#define PIRQ_PMON 0x16 /* Performance Monitor */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#define PIRQ_SD 0x17 /* SD */
#endif
#define PIRQ_IMC0 0x20 /* IMC INT0 */
@@ -69,7 +69,7 @@
#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */
#define PIRQ_IDE 0x40 /* IDE 14h.1 */
#define PIRQ_SATA 0x41 /* SATA 11h.0 */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define PIRQ_SD 0x42 /* SD 14h.7 */
#define PIRQ_GPP0 0x50 /* GPP INT 0 */
#define PIRQ_GPP1 0x51 /* GPP INT 1 */

4
src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
View File

@@ -16,7 +16,7 @@
#ifndef AMD_PCI_INT_TYPES_H
#define AMD_PCI_INT_TYPES_H
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
const char *intr_types[] = {
[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
@@ -26,7 +26,7 @@ const char *intr_types[] = {
[0x40] = "IDE\t", "SATA\t",
[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
};
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
const char *intr_types[] = {
[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",

4
src/southbridge/amd/agesa/hudson/fadt.c
View File

@@ -27,7 +27,7 @@
#include "hudson.h"
#include "smi.h"
#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE)
#if CONFIG(HUDSON_LEGACY_FREE)
#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
#else
#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
@@ -71,7 +71,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->preferred_pm_profile = FADT_PM_PROFILE;
fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
if (CONFIG(HAVE_SMI_HANDLER)) {
fadt->smi_cmd = ACPI_SMI_CTL_PORT;
fadt->acpi_enable = ACPI_SMI_CMD_ENABLE;
fadt->acpi_disable = ACPI_SMI_CMD_DISABLE;

6
src/southbridge/amd/agesa/hudson/hudson.c
View File

@@ -154,7 +154,7 @@ static void hudson_init_acpi_ports(void)
/* CpuControl is in \_PR.CP00, 6 bytes */
pm_write16(0x66, ACPI_CPU_CONTROL);
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
if (CONFIG(HAVE_SMI_HANDLER)) {
pm_write16(0x6a, ACPI_SMI_CTL_PORT);
hudson_enable_acpi_cmd_smi();
} else {
@@ -175,8 +175,8 @@ static void hudson_init(void *chip_info)
static void hudson_final(void *chip_info)
{
/* AMD AGESA does not enable thermal zone, so we enable it here. */
if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM) &&
!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE))
if (CONFIG(HUDSON_IMC_FWM) &&
!CONFIG(ACPI_ENABLE_THERMAL_ZONE))
enable_imc_thermal_zone();
}

4
src/southbridge/amd/agesa/hudson/imc.c
View File

@@ -35,7 +35,7 @@ void imc_reg_init(void)
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff);
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06);
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7);
@@ -43,7 +43,7 @@ void imc_reg_init(void)
write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff);
#endif
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
UINT8 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;

2
src/southbridge/amd/agesa/hudson/lpc.c
View File

@@ -343,7 +343,7 @@ static struct device_operations lpc_ops = {
.read_resources = hudson_lpc_read_resources,
.set_resources = hudson_lpc_set_resources,
.enable_resources = hudson_lpc_enable_resources,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,

4
src/southbridge/amd/agesa/hudson/pci_devs.h
View File

@@ -68,7 +68,7 @@
#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
/* IDE */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define IDE_DEV 0x14
#define IDE_FUNC 1
# define IDE_DEVID 0x780C
@@ -101,7 +101,7 @@
#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
/* PCIe Ports */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define SB_PCIE_DEV 0x15
#define SB_PCIE_PORT1_FUNC 0
#define SB_PCIE_PORT2_FUNC 1

2
src/southbridge/amd/agesa/hudson/resume.c
View File

@@ -104,7 +104,7 @@ static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable;
FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail;
FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci1Enable = FALSE;
#if DUMP_FCH_SETTING

2
src/southbridge/amd/agesa/hudson/sata.c
View File

@@ -23,7 +23,7 @@
static void sata_init(struct device *dev)
{
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
/**************************************
* Configure the SATA port multiplier *
**************************************/

8
src/southbridge/amd/agesa/hudson/spi.c
View File

@@ -36,7 +36,7 @@
#define SPI_REG_CNTRL11 0xd
#define CNTRL11_FIFOPTR_MASK 0x07
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#define AMD_SB_SPI_TX_LEN 64
#else
#define AMD_SB_SPI_TX_LEN 8
@@ -110,7 +110,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
readoffby1 = bytesout ? 0 : 1;
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
spi_write(0x1E, 5);
spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */
spi_write(0x1E, 6);
@@ -144,7 +144,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
int chipset_volatile_group_begin(const struct spi_flash *flash)
{
if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM))
if (!CONFIG(HUDSON_IMC_FWM))
return 0;
ImcSleep(NULL);
@@ -153,7 +153,7 @@ int chipset_volatile_group_begin(const struct spi_flash *flash)
int chipset_volatile_group_end(const struct spi_flash *flash)
{
if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM))
if (!CONFIG(HUDSON_IMC_FWM))
return 0;
ImcWakeup(NULL);

4
src/southbridge/amd/amd8111/acpi.c
View File

@@ -99,7 +99,7 @@ static int lsmbus_block_write(struct device *dev, uint8_t cmd, u8 bytes,
}
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
unsigned pm_base;
#endif
@@ -171,7 +171,7 @@ static void acpi_init(struct device *dev)
(on * 12) + (on >> 1), (on & 1) * 5);
}
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
pm_base = pci_read_config16(dev, 0x58) & 0xff00;
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
#endif

2
src/southbridge/amd/amd8111/acpi/sleepstates.asl
View File

@@ -14,7 +14,7 @@
*/
/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#if CONFIG(HAVE_ACPI_RESUME)
Name (SSFG, 0x05)
#else
Name (SSFG, 0x01)

8
src/southbridge/amd/amd8111/lpc.c
View File

@@ -23,7 +23,7 @@
#include <pc80/isa-dma.h>
#include <cpu/x86/lapic.h>
#include <arch/ioapic.h>
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <cpu/amd/powernow.h>
@@ -131,7 +131,7 @@ static void lpci_set_subsystem(struct device *dev, unsigned int vendor,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
extern u16 pm_base;
@@ -142,7 +142,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
}
static void southbridge_acpi_fill_ssdt_generator(struct device *device) {
#if IS_ENABLED(CONFIG_SET_FIDVID)
#if CONFIG(SET_FIDVID)
amd_generate_powernow(pm_base + 0x10, 6, 1);
acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
#endif
@@ -160,7 +160,7 @@ static struct device_operations lpc_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = lpc_init,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
.acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,
#endif

2
src/southbridge/amd/cimx/sb800/SBPLATFORM.h
View File

@@ -49,7 +49,7 @@ typedef union _PCI_ADDR {
#endif
#define FIXUP_PTR(ptr) ptr
#if IS_ENABLED(CONFIG_SB800_IMC_FWM)
#if CONFIG(SB800_IMC_FWM)
#define IMC_ENABLE_OVER_WRITE 0x01
#endif

2
src/southbridge/amd/cimx/sb800/bootblock.c
View File

@@ -100,7 +100,7 @@ static void enable_clocks(void)
// change twice.
reg32 = *acpi_mmio;
reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default)
#if !IS_ENABLED(CONFIG_SUPERIO_WANTS_14MHZ_CLOCK)
#if !CONFIG(SUPERIO_WANTS_14MHZ_CLOCK)
reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz
#endif
*acpi_mmio = reg32;

6
src/southbridge/amd/cimx/sb800/late.c
View File

@@ -163,7 +163,7 @@ static struct device_operations lpc_ops = {
.read_resources = lpc_read_resources,
.set_resources = lpc_set_resources,
.enable_resources = pci_dev_enable_resources,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,
@@ -386,9 +386,9 @@ static void sb800_enable(struct device *dev)
case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */
/* Initialize the fans */
#if IS_ENABLED(CONFIG_SB800_IMC_FAN_CONTROL)
#if CONFIG(SB800_IMC_FAN_CONTROL)
init_sb800_IMC_fans(dev);
#elif IS_ENABLED(CONFIG_SB800_MANUAL_FAN_CONTROL)
#elif CONFIG(SB800_MANUAL_FAN_CONTROL)
init_sb800_MANUAL_fans(dev);
#endif
break;

4
src/southbridge/amd/cimx/sb800/spi.c
View File

@@ -135,7 +135,7 @@ static void ImcWakeup(void)
int chipset_volatile_group_begin(const struct spi_flash *flash)
{
if (!IS_ENABLED(CONFIG_SB800_IMC_FWM))
if (!CONFIG(SB800_IMC_FWM))
return 0;
ImcSleep();
@@ -144,7 +144,7 @@ int chipset_volatile_group_begin(const struct spi_flash *flash)
int chipset_volatile_group_end(const struct spi_flash *flash)
{
if (!IS_ENABLED(CONFIG_SB800_IMC_FWM))
if (!CONFIG(SB800_IMC_FWM))
return 0;
ImcWakeup();

2
src/southbridge/amd/cimx/sb900/late.c
View File

@@ -113,7 +113,7 @@ static struct device_operations lpc_ops = {
.set_resources = lpc_set_resources,
.enable_resources = lpc_enable_resources,
.init = lpc_init,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
.scan_bus = scan_lpc_bus,

2
src/southbridge/amd/common/acpi/sleepstates.asl
View File

@@ -15,7 +15,7 @@
*/
/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#if CONFIG(HAVE_ACPI_RESUME)
Name (SSFG, 0x0D)
#else
Name (SSFG, 0x09)

8
src/southbridge/amd/pi/hudson/acpi/fch.asl
View File

@@ -47,7 +47,7 @@ Device(SBUS) {
#include "usb.asl"
/* 0:14.2 - HD Audio */
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
#if !CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
#include "audio.asl"
#endif
@@ -129,7 +129,7 @@ Method(_CRS, 0) {
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
#if CONFIG(HUDSON_IMC_FWM)
/* TODO: It is unstable.
* might be fixed by restructuring
*/
@@ -161,8 +161,8 @@ Method(_INI, 0) {
/* Determine the OS we're running on */
OSFL()
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
#if CONFIG(HUDSON_IMC_FWM)
#if CONFIG(ACPI_ENABLE_THERMAL_ZONE)
ITZE() /* enable IMC Fan Control*/
#endif
#endif

8
src/southbridge/amd/pi/hudson/acpi/usb.asl
View File

@@ -50,8 +50,8 @@ Device(UOH6) {
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && \
!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) && \
!CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
/* 0:14.5 - OHCI */
Device(UEH1) {
Name(_ADR, 0x00140005)
@@ -65,8 +65,8 @@ Device(XHC0) {
Name(_PRW, Package() {0x0B, 4})
} /* end XHC0 */
#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && \
!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) && \
!CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
/* 0:10.1 - XHCI 1*/
Device(XHC1) {
Name(_ADR, 0x00100001)

6
src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
View File

@@ -63,12 +63,12 @@
#define PIRQ_IDE 0x40 /* IDE 14h.1 */
#define PIRQ_SATA 0x41 /* SATA 11h.0 */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON)
#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON)
#define FCH_INT_TABLE_SIZE 0x63
#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
#endif
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
#define FCH_INT_TABLE_SIZE 0x54
#define PIRQ_GPP0 0x50 /* GPP INT 0 */
#define PIRQ_GPP1 0x51 /* GPP INT 1 */
@@ -76,7 +76,7 @@
#define PIRQ_GPP3 0x53 /* GPP INT 3 */
#endif
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
#if CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
#define FCH_INT_TABLE_SIZE 0x76
#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
#define PIRQ_I2C0 0x70

6
src/southbridge/amd/pi/hudson/amd_pci_int_types.h
View File

@@ -23,13 +23,13 @@ const char *intr_types[] = {
[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
[0x7F] = "RSVD\t",
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON)
#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON)
[0x40] = "RSVD\t", "SATA\t",
[0x60] = "RSVD\t", "RSVD\t", "GPIO\t",
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
#elif CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
[0x40] = "IDE\t", "SATA\t",
[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
#elif CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
[0x40] = "IDE\t", "SATA\t",
[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
[0x62] = "GPIO\t",

2
src/southbridge/amd/pi/hudson/early_setup.c
View File

@@ -27,7 +27,7 @@
#include "pci_devs.h"
#include <Fch/Fch.h>
#if IS_ENABLED(CONFIG_HUDSON_UART)
#if CONFIG(HUDSON_UART)
#include <cpu/x86/msr.h>
#include <delay.h>

4
src/southbridge/amd/pi/hudson/fadt.c
View File

@@ -27,7 +27,7 @@
#include "hudson.h"
#include "smi.h"
#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE)
#if CONFIG(HUDSON_LEGACY_FREE)
#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
#else
#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
@@ -63,7 +63,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->preferred_pm_profile = FADT_PM_PROFILE;
fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
if (CONFIG(HAVE_SMI_HANDLER)) {
fadt->smi_cmd = ACPI_SMI_CTL_PORT;
fadt->acpi_enable = ACPI_SMI_CMD_ENABLE;
fadt->acpi_disable = ACPI_SMI_CMD_DISABLE;

4
src/southbridge/amd/pi/hudson/gpio.h
View File

@@ -25,7 +25,7 @@
#define GPIO_OUTPUT_VALUE (1 << 22)
#define GPIO_OUTPUT_ENABLE (1 << 23)
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
#if CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
/* GPIO_0 - GPIO_62 */
#define GPIO_BANK0_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1500)
#define GPIO_0 (GPIO_BANK0_CONTROL + 0x00)
@@ -124,7 +124,7 @@
#define GPIO_146 (GPIO_BANK2_CONTROL + 0x48)
#define GPIO_147 (GPIO_BANK2_CONTROL + 0x4C)
#define GPIO_148 (GPIO_BANK2_CONTROL + 0x50)
#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) */
#endif /* CONFIG(SOUTHBRIDGE_AMD_PI_KERN) */
typedef uint32_t gpio_t;

6
src/southbridge/amd/pi/hudson/hudson.c
View File

@@ -99,7 +99,7 @@ static void hudson_init_acpi_ports(void)
/* CpuControl is in \_PR.CP00, 6 bytes */
pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
if (CONFIG(HAVE_SMI_HANDLER)) {
pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT);
hudson_enable_acpi_cmd_smi();
} else {
@@ -119,9 +119,9 @@ static void hudson_init(void *chip_info)
static void hudson_final(void *chip_info)
{
if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
if (CONFIG(HUDSON_IMC_FWM)) {
agesawrapper_fchecfancontrolservice();
if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE))
if (!CONFIG(ACPI_ENABLE_THERMAL_ZONE))
enable_imc_thermal_zone();
}
}

2
src/southbridge/amd/pi/hudson/hudson.h
View File

@@ -191,7 +191,7 @@ void lpc_wideio_16_window(uint16_t base);
void hudson_tpm_decode_spi(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
#if IS_ENABLED(CONFIG_HUDSON_UART)
#if CONFIG(HUDSON_UART)
void configure_hudson_uart(void);
#endif

4
src/southbridge/amd/pi/hudson/lpc.c
View File

@@ -86,7 +86,7 @@ static void lpc_init(struct device *dev)
/* Set up SERIRQ, enable continuous mode */
byte = (BIT(4) | BIT(7));
if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
byte |= BIT(6);
pm_write8(PM_SERIRQ_CONF, byte);
@@ -353,7 +353,7 @@ static struct device_operations lpc_ops = {
.read_resources = hudson_lpc_read_resources,
.set_resources = hudson_lpc_set_resources,
.enable_resources = hudson_lpc_enable_resources,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,

4
src/southbridge/amd/pi/hudson/pci_devs.h
View File

@@ -71,7 +71,7 @@
#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
/* IDE */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
#define IDE_DEV 0x14
#define IDE_FUNC 1
#define IDE_DEVID 0x780C
@@ -104,7 +104,7 @@
#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
/* PCIe Ports */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
#define SB_PCIE_DEV 0x15
#define SB_PCIE_PORT1_FUNC 0
#define SB_PCIE_PORT2_FUNC 1

2
src/southbridge/amd/pi/hudson/sata.c
View File

@@ -23,7 +23,7 @@
static void sata_init(struct device *dev)
{
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
/**************************************
* Configure the SATA port multiplier *
**************************************/

2
src/southbridge/amd/rs780/cmn.c
View File

@@ -342,7 +342,7 @@ u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port)
void rs780_set_tom(struct device *nb_dev)
{
/* set TOM */
#if IS_ENABLED(CONFIG_GFXUMA)
#if CONFIG(GFXUMA)
pci_write_config32(nb_dev, 0x90, uma_memory_base);
//nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
#else

10
src/southbridge/amd/rs780/early_setup.c
View File

@@ -105,7 +105,7 @@ static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
}
}
/* family 10 only, for reg > 0xFF */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos,
u32 mask, u32 val)
{
@@ -151,7 +151,7 @@ static u8 is_famly10(void)
return (cpuid_eax(1) & 0xff00000) != 0;
}
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
static u8 l3_cache(void)
{
return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
@@ -231,7 +231,7 @@ void rs780_htinit(void)
} else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
printk(BIOS_INFO, "rs780_htinit: HT3 mode\n");
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
/* HT3 mode, RPR 8.4.3 */
set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);
@@ -271,7 +271,7 @@ void rs780_htinit(void)
}
}
#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
#if !CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
/*******************************************************
* Optimize k8 with UMA.
* See BKDG_NPT_0F guide for details.
@@ -327,7 +327,7 @@ static void k8_optimization(void)
#define k8_optimization() do {} while (0)
#endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
static void fam10_optimization(void)
{
pci_devfn_t cpu_f0, cpu_f2, cpu_f3;

10
src/southbridge/amd/rs780/gfx.c
View File

@@ -380,7 +380,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* GFX_InitFBAccess finished. */
#if IS_ENABLED(CONFIG_GFXUMA) /* for UMA mode. */
#if CONFIG(GFXUMA) /* for UMA mode. */
/* GFX_StartMC. */
set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
@@ -442,7 +442,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
vgainfo.sHeader.ucTableFormatRevision = 1;
vgainfo.sHeader.ucTableContentRevision = 2;
#if !IS_ENABLED(CONFIG_GFXUMA) /* SP mode. */
#if !CONFIG(GFXUMA) /* SP mode. */
// Side port support is incomplete, do not use it
// These parameters must match the motherboard
vgainfo.ulBootUpSidePortClock = 667*100;
@@ -627,7 +627,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* Transfer the Table to VBIOS. */
pointer = (u32 *)&vgainfo;
for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {
#if IS_ENABLED(CONFIG_GFXUMA)
#if CONFIG(GFXUMA)
*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
#else
*GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
@@ -756,7 +756,7 @@ static void rs780_internal_gfx_enable(struct device *dev)
struct device *nb_dev = pcidev_on_root(0x0, 0);
msr_t sysmem;
#if !IS_ENABLED(CONFIG_GFXUMA)
#if !CONFIG(GFXUMA)
u32 FB_Start, FB_End;
#endif
@@ -799,7 +799,7 @@ static void rs780_internal_gfx_enable(struct device *dev)
set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
#if IS_ENABLED(CONFIG_GFXUMA)
#if CONFIG(GFXUMA)
/* GFX_InitUMA. */
/* Copy CPU DDR Controller to NB MC. */
struct device *k8_f1 = pcidev_on_root(0x18, 1);

2
src/southbridge/amd/rs780/rs780.c
View File

@@ -204,7 +204,7 @@ static void rs780_nb_gfx_dev_table(struct device *nb_dev, struct device *dev)
/* Program Straps. */
romstrap2 = 1 << 26; // enables audio function
#if IS_ENABLED(CONFIG_GFXUMA)
#if CONFIG(GFXUMA)
// bits 7-9: aperture size
// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;

4
src/southbridge/amd/sb700/bootblock.c
View File

@@ -44,7 +44,7 @@ static void sb700_enable_rom(void)
dev = PCI_DEV(0, 0x14, 3);
reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
if (IS_ENABLED(CONFIG_SPI_FLASH))
if (CONFIG(SPI_FLASH))
/* Disable decode of variable LPC ROM address ranges 1 and 2. */
reg8 &= ~((1 << 3) | (1 << 4));
else
@@ -100,7 +100,7 @@ static void sb700_configure_rom(void)
dev = PCI_DEV(0, 0x14, 3);
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) {
if (CONFIG(SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) {
uint32_t prev_spi_cfg;
volatile uint32_t *spi_mmio;

20
src/southbridge/amd/sb700/early_setup.c
View File

@@ -151,7 +151,7 @@ void sb7xx_51xx_lpc_init(void)
reg32 |= 1 << 20;
pci_write_config32(dev, 0x64, reg32);
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
post_code(0x66);
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
reg8 = pci_read_config8(dev, 0xBB);
@@ -165,7 +165,7 @@ void sb7xx_51xx_lpc_init(void)
// XXX Serial port decode on LPC is hardcoded to 0x3f8
reg8 = pci_read_config8(dev, 0x44);
reg8 |= 1 << 6;
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG_TTYS0_BASE == 0x2f8
reg8 |= 1 << 7;
#endif
@@ -404,7 +404,7 @@ static void sb700_devices_por_init(void)
printk(BIOS_INFO, "%s: Secondary SMBUS controller I/O not found\n", __func__);
}
else {
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) {
if (CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) {
/* Disable legacy sensor support / reset ASF Slave state machine per RPR 2.27 step 3 */
outb(0x40, SMBUS_AUX_IO_BASE + SMBSLVMISC);
}
@@ -459,7 +459,7 @@ static void sb700_devices_por_init(void)
/*pci_write_config8(dev, 0x79, 0x4F); */
pci_write_config8(dev, 0x78, 0xFF);
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) {
if (CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) {
printk(BIOS_DEBUG, "%s: Disabling ISA DMA support\n", __func__);
/* Disable LPC ISA DMA Capability */
byte = pci_read_config8(dev, 0x78);
@@ -484,7 +484,7 @@ static void sb700_devices_por_init(void)
/* LPC Device, BDF:0-20-3 */
printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
if (!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) {
if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) {
/* DMA enable */
pci_write_config8(dev, 0x40, 0x04);
}
@@ -531,7 +531,7 @@ static void sb700_devices_por_init(void)
pci_write_config8(dev, 0x50, 0x01);
if (!sata_ahci_mode){
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* SP5100 default SATA mode is RAID5 MODE */
dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0);
@@ -597,7 +597,7 @@ static void sb700_pmio_por_init(void)
uint8_t enable_c_states;
enable_c_states = 0;
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
if (get_option(&byte, "cpu_c_states") == CB_SUCCESS)
enable_c_states = !!byte;
#endif
@@ -608,7 +608,7 @@ static void sb700_pmio_por_init(void)
byte |= 0x20;
pmio_write(0x66, byte);
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) {
if (CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) {
/* RPR 2.11 Sx State Settings */
byte = pmio_read(0x65);
byte &= ~(1 << 7); /* SpecialFunc = 0 */
@@ -687,7 +687,7 @@ static void sb700_pmio_por_init(void)
byte |= 0xc0;
pmio_write(0xbb, byte);
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* RPR 2.26 Alter CPU reset timing */
byte = pmio_read(0xb2);
byte |= 0x1 << 2; /* Enable CPU reset timing option */
@@ -736,7 +736,7 @@ static void sb700_pci_cfg(void)
* mentioned in RPR. But I keep them. The registers and the
* comments are compatible. */
dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
if (!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) {
if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) {
/* Enabling LPC DMA function. */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);

2
src/southbridge/amd/sb700/fadt.c
View File

@@ -155,7 +155,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->x_gpe1_blk.addrl = 0;
fadt->x_gpe1_blk.addrh = 0x0;
if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
if (CONFIG(CPU_AMD_MODEL_10XXX))
amd_powernow_update_fadt(fadt);
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));

10
src/southbridge/amd/sb700/lpc.c
View File

@@ -45,13 +45,13 @@ static void lpc_init(struct device *dev)
pci_write_config32(sm_dev, 0x64, dword);
/* Initialize isa dma */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT)
#if CONFIG(SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT)
printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
#else
isa_dma_init();
#endif
if (!IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) {
if (!CONFIG(SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA)) {
/* Enable DMA transaction on the LPC bus */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
@@ -66,7 +66,7 @@ static void lpc_init(struct device *dev)
/* Disable LPC MSI Capability */
byte = pci_read_config8(dev, 0x78);
byte &= ~(1 << 1);
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* Disable FlowContrl, Always service the request from Host
* whenever there is a request from Host pending
*/
@@ -246,7 +246,7 @@ static void sb700_lpc_enable_resources(struct device *dev)
sb700_lpc_enable_childrens_resources(dev);
}
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
static void southbridge_acpi_fill_ssdt_generator(struct device *device) {
amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1);
@@ -275,7 +275,7 @@ static struct device_operations lpc_ops = {
.read_resources = sb700_lpc_read_resources,
.set_resources = sb700_lpc_set_resources,
.enable_resources = sb700_lpc_enable_resources,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = lpc_acpi_name,
.write_acpi_tables = acpi_write_hpet,
.acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,

2
src/southbridge/amd/sb700/sata.c
View File

@@ -351,7 +351,7 @@ static void sata_init(struct device *dev)
byte |= 7 << 0;
pci_write_config8(dev, 0x4, byte);
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* Master Latency Timer */
pci_write_config32(dev, 0xC, 0x00004000);
#endif

2
src/southbridge/amd/sb700/sb700.c
View File

@@ -222,7 +222,7 @@ void sb7xx_51xx_enable(struct device *dev)
}
}
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
struct chip_operations southbridge_amd_sb700_ops = {
CHIP_NAME("ATI SP5100")
.enable_dev = sb7xx_51xx_enable,

4
src/southbridge/amd/sb700/sm.c
View File

@@ -136,7 +136,7 @@ static void sm_init(struct device *dev)
pci_write_config8(dev, 0x41, byte);
byte = pm_ioread(0x61);
if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
if (CONFIG(CPU_AMD_MODEL_10XXX))
byte &= ~(1 << 1); /* Clear for non-K8 CPUs */
else
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
@@ -305,7 +305,7 @@ static void sm_init(struct device *dev)
pci_write_config32(dev, SB_MMIO_CFG_REG, dword);
}
byte = pci_read_config8(dev, 0xAE);
if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
if (CONFIG(ENABLE_APIC_EXT_ID))
byte |= 1 << 4;
byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */
byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */

2
src/southbridge/amd/sb700/usb.c
View File

@@ -181,7 +181,7 @@ static void usb_init2(struct device *dev)
dword |= 1 << 8;
dword &= ~(1 << 27); /* 6.23 */
}
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
#if CONFIG(SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
/* SP5100 Erratum 36 */
dword &= ~(1 << 26);
if (!ehci_async_data_cache)

2
src/southbridge/amd/sb800/fadt.c
View File

@@ -155,7 +155,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->x_gpe1_blk.addrl = 0;
fadt->x_gpe1_blk.addrh = 0x0;
if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
if (CONFIG(CPU_AMD_MODEL_10XXX))
amd_powernow_update_fadt(fadt);
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));

2
src/southbridge/amd/sb800/lpc.c
View File

@@ -245,7 +245,7 @@ static struct device_operations lpc_ops = {
.read_resources = sb800_lpc_read_resources,
.set_resources = sb800_lpc_set_resources,
.enable_resources = sb800_lpc_enable_resources,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,

6
src/southbridge/amd/sr5650/early_setup.c
View File

@@ -57,7 +57,7 @@ static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev,
u32 reg_old, reg;
/* family 10 only, for reg > 0xFF */
if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10))
if (!CONFIG(NORTHBRIDGE_AMD_AMDFAM10))
return;
reg = reg_old = pci_read_config32(fam10_dev, reg_pos);
@@ -222,7 +222,7 @@ void sr5650_htinit(void)
/* Enable Protocol checker */
set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC);
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
/* HT3 mode, RPR 5.4.3 */
set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0);
@@ -307,7 +307,7 @@ void fam10_optimization(void)
msr_t msr;
u32 val;
if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10))
if (!CONFIG(NORTHBRIDGE_AMD_AMDFAM10))
return;
printk(BIOS_INFO, "fam10_optimization()\n");

4
src/southbridge/amd/sr5650/ht.c
View File

@@ -155,7 +155,7 @@ static void pcie_init(struct device *dev)
static void sr5690_read_resource(struct device *dev)
{
if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
if (CONFIG(EXT_CONF_SUPPORT)) {
printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev));
set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */
}
@@ -174,7 +174,7 @@ static void sr5690_set_resources(struct device *dev)
{
pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
if (CONFIG(EXT_CONF_SUPPORT)) {
uint32_t reg;
struct device *amd_ht_cfg_dev;
struct device *amd_addr_map_dev;

2
src/southbridge/amd/sr5650/sr5650.c
View File

@@ -808,7 +808,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
struct resource *res;
resource_t mmconf_base = EXT_CONF_BASE_ADDRESS;
if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
if (CONFIG(EXT_CONF_SUPPORT)) {
res = sr5650_retrieve_cpu_mmio_resource();
if (res)
mmconf_base = res->base;