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coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

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This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julius Werner
2019-03-05 16:53:33 -08:00
committed by Patrick Georgi
parent b3a8cc54db
commit cd49cce7b7
920 changed files with 2285 additions and 2285 deletions
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8
src/southbridge/intel/ibexpeak/lpc.c
View File

@@ -74,7 +74,7 @@ static void pch_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@@ -283,7 +283,7 @@ static void pch_rtc_init(struct device *dev)
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
#if IS_ENABLED(CONFIG_ELOG)
#if CONFIG(ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}
@@ -798,8 +798,8 @@ static void southbridge_fill_ssdt(struct device *device)
static void lpc_final(struct device *dev)
{
/* Call SMM finalize() handlers before resume */
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) ||
if (CONFIG(HAVE_SMI_HANDLER)) {
if (CONFIG(INTEL_CHIPSET_LOCKDOWN) ||
acpi_is_wakeup_s3()) {
outb(APM_CNT_FINALIZE, APM_CNT);
}

8
src/southbridge/intel/ibexpeak/me.c
View File

@@ -40,7 +40,7 @@
#include "me.h"
#include "pch.h"
#if IS_ENABLED(CONFIG_CHROMEOS)
#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -59,7 +59,7 @@ static const char *me_bios_path_values[] = {
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
#if CONFIG(DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -470,7 +470,7 @@ static me_bios_path intel_me_path(struct device *dev)
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
#if IS_ENABLED(CONFIG_ELOG)
#if CONFIG(ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -559,7 +559,7 @@ static int intel_me_extend_valid(struct device *dev)
}
printk(BIOS_DEBUG, "\n");
#if IS_ENABLED(CONFIG_CHROMEOS)
#if CONFIG(CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif

2
src/southbridge/intel/ibexpeak/pch.h
View File

@@ -62,7 +62,7 @@ int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void gpi_route_interrupt(u8 gpi, u8 mode);
#if IS_ENABLED(CONFIG_ELOG)
#if CONFIG(ELOG)
void pch_log_state(void);
#endif
#else /* __PRE_RAM__ */

2
src/southbridge/intel/ibexpeak/smi.c
View File

@@ -228,7 +228,7 @@ void southbridge_smm_init(void)
u16 pm1_en;
u32 gpe0_en;
#if IS_ENABLED(CONFIG_ELOG)
#if CONFIG(ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif

8
src/southbridge/intel/ibexpeak/smihandler.c
View File

@@ -430,7 +430,7 @@ static void southbridge_smi_sleep(void)
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
#if IS_ENABLED(CONFIG_ELOG_GSMI)
#if CONFIG(ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -532,7 +532,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
#if IS_ENABLED(CONFIG_ELOG_GSMI)
#if CONFIG(ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -604,7 +604,7 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
#if IS_ENABLED(CONFIG_ELOG_GSMI)
#if CONFIG(ELOG_GSMI)
case APM_CNT_ELOG_GSMI:
southbridge_smi_gsmi();
break;
@@ -628,7 +628,7 @@ static void southbridge_smi_pm1(void)
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
#if IS_ENABLED(CONFIG_ELOG_GSMI)
#if CONFIG(ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);