coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/arch/arm/armv7/mmu.c

@@ -37,7 +37,7 @@
 
 #include <arch/cache.h>
 
-#if IS_ENABLED(CONFIG_ARM_LPAE)
+#if CONFIG(ARM_LPAE)
 /* See B3.6.2 of ARMv7 Architecture Reference Manual */
 /* TODO: Utilize the contiguous hint flag */
 #define ATTR_BLOCK (\
@@ -170,7 +170,7 @@ static pte_t *mmu_create_subtable(pte_t *pgd_entry)
 	/* Initialize the new subtable with entries of the same attributes
 	 * (XN bit moves from 4 to 0, set PAGE unless block was unmapped). */
 	pte_t attr = *pgd_entry & ~(BLOCK_MASK);
-	if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4)))
+	if (!CONFIG(ARM_LPAE) && (attr & (1 << 4)))
 		attr = ((attr & ~(1 << 4)) | (1 << 0));
 	if (attr & ATTR_BLOCK)
 		attr = (attr & ~ATTR_BLOCK) | ATTR_PAGE;
@@ -208,7 +208,7 @@ void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy)
 
 	/* Always _one_ _damn_ bit that won't fit... (XN moves from 4 to 0) */
 	pte_t attr = attrs[policy].value;
-	if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4)))
+	if (!CONFIG(ARM_LPAE) && (attr & (1 << 4)))
 		attr = ((attr & ~(1 << 4)) | (1 << 0));
 
 	/* Mask away high address bits that are handled by upper level table. */

src/arch/arm/include/arch/memlayout.h

@@ -18,16 +18,16 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-#define SUPERPAGE_SIZE ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M)
+#define SUPERPAGE_SIZE ((1 + CONFIG(ARM_LPAE)) * 1M)
 
 #define TTB(addr, size) \
 	REGION(ttb, addr, size, 16K) \
-	_ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \
+	_ = ASSERT(size >= 16K + CONFIG(ARM_LPAE) * 32, \
 		"TTB must be 16K (+ 32 for LPAE)!");
 
 #define TTB_SUBTABLES(addr, size) \
-	REGION(ttb_subtables, addr, size, IS_ENABLED(CONFIG_ARM_LPAE)*3K + 1K) \
-	_ = ASSERT(size % (1K + 3K * IS_ENABLED(CONFIG_ARM_LPAE)) == 0, \
+	REGION(ttb_subtables, addr, size, CONFIG(ARM_LPAE)*3K + 1K) \
+	_ = ASSERT(size % (1K + 3K * CONFIG(ARM_LPAE)) == 0, \
 		"TTB subtable region must be evenly divisible by table size!");
 
 /* ARM stacks need 8-byte alignment and stay in one place through ramstage. */

src/arch/arm/include/armv7/arch/cache.h

@@ -134,7 +134,7 @@ static inline void write_mair0(uint32_t val)
 /* write translation table base register 0 (TTBR0) */
 static inline void write_ttbr0(uint32_t val)
 {
-	if (IS_ENABLED(CONFIG_ARM_LPAE))
+	if (CONFIG(ARM_LPAE))
 		asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : :
 			[val] "r" (val), [zero] "r" (0));
 	else

src/arch/arm/tables.c

@@ -32,7 +32,7 @@ void bootmem_arch_add_ranges(void)
 	bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables),
 			  BM_MEM_RAMSTAGE);
 
-	if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
+	if (!CONFIG(COMMON_CBFS_SPI_WRAPPER))
 		return;
 	bootmem_add_range((uintptr_t)_postram_cbfs_cache,
 			  REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);

src/arch/arm64/arm_tf.c

@@ -56,7 +56,7 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
 
 	SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0);
 
-	if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_OS)) {
+	if (CONFIG(ARM64_USE_SECURE_OS)) {
 		struct prog bl32 = PROG_INIT(PROG_BL32,
 					     CONFIG_CBFS_PREFIX"/secure_os");
 

src/arch/arm64/armv8/exception.c

@@ -220,7 +220,7 @@ void exception_init(void)
 	printk(BIOS_DEBUG, "ARM64: Exception handlers installed.\n");
 
 	/* Only spend time testing on debug builds that are trying to detect more errors. */
-	if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) {
+	if (CONFIG(FATAL_ASSERTS)) {
 		printk(BIOS_DEBUG, "ARM64: Testing exception\n");
 		test_exception();
 		printk(BIOS_DEBUG, "ARM64: Done test exception\n");

src/arch/arm64/boot.c

@@ -30,7 +30,7 @@ static void run_payload(struct prog *prog)
 	arg = prog_entry_arg(prog);
 	u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L);
 
-	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE))
+	if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
 		arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr);
 	else
 		transition_to_el2(doit, arg, payload_spsr);

src/arch/arm64/include/armv8/arch/barrier.h

@@ -30,7 +30,7 @@
 #define rmb()		asm volatile("dsb ld" : : : "memory")
 #define wmb()		asm volatile("dsb st" : : : "memory")
 
-#if IS_ENABLED(CONFIG_SMP)
+#if CONFIG(SMP)
 #define barrier() __asm__ __volatile__("": : :"memory")
 #endif
 

src/arch/arm64/tables.c

@@ -30,12 +30,12 @@ void bootmem_arch_add_ranges(void)
 {
 	bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE);
 
-	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) &&
+	if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE) &&
 	    REGION_SIZE(bl31) > 0)
 		bootmem_add_range((uintptr_t)_bl31, REGION_SIZE(bl31),
 				  BM_MEM_BL31);
 
-	if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
+	if (!CONFIG(COMMON_CBFS_SPI_WRAPPER))
 		return;
 	bootmem_add_range((uintptr_t)_postram_cbfs_cache,
 			  REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);

src/arch/mips/bootblock_simple.c

@@ -26,7 +26,7 @@ void main(void)
 	/* Mainboard basic init */
 	bootblock_mainboard_init();
 
-#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)
+#if CONFIG(BOOTBLOCK_CONSOLE)
 	console_init();
 #endif
 

src/arch/ppc64/include/arch/cpu.h

@@ -31,7 +31,7 @@ struct thread;
 struct cpu_info {
 	struct device *cpu;
 	unsigned long index;
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
 	struct thread *thread;
 #endif
 };

src/arch/riscv/include/arch/cpu.h

@@ -33,7 +33,7 @@ struct thread;
 struct cpu_info {
 	struct device *cpu;
 	unsigned long index;
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
 	struct thread *thread;
 #endif
 };

src/arch/riscv/sbi.c

@@ -45,7 +45,7 @@ static uintptr_t sbi_set_timer(uint64_t when)
 	return 0;
 }
 
-#if IS_ENABLED(CONFIG_CONSOLE_SERIAL)
+#if CONFIG(CONSOLE_SERIAL)
 static uintptr_t sbi_console_putchar(uint8_t ch)
 {
 	uart_tx_byte(CONFIG_UART_FOR_CONSOLE, ch);
@@ -86,7 +86,7 @@ void handle_sbi(trapframe *tf)
 		ret = sbi_set_timer(arg0);
 #endif
 		break;
-#if IS_ENABLED(CONFIG_CONSOLE_SERIAL)
+#if CONFIG(CONSOLE_SERIAL)
 	case SBI_CONSOLE_PUTCHAR:
 		ret = sbi_console_putchar(arg0);
 		break;

src/arch/x86/acpi.c

@@ -1066,7 +1066,7 @@ void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length)
 	header->checksum = acpi_checksum((void *)bert, header->length);
 }
 
-#if IS_ENABLED(CONFIG_COMMON_FADT)
+#if CONFIG(COMMON_FADT)
 void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
@@ -1088,11 +1088,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	fadt->x_dsdt_l = (unsigned long)dsdt;
 	fadt->x_dsdt_h = 0;
 
-	if (IS_ENABLED(CONFIG_SYSTEM_TYPE_CONVERTIBLE) ||
-	    IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP))
+	if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) ||
+	    CONFIG(SYSTEM_TYPE_LAPTOP))
 		fadt->preferred_pm_profile = PM_MOBILE;
-	else if (IS_ENABLED(CONFIG_SYSTEM_TYPE_DETACHABLE) ||
-		 IS_ENABLED(CONFIG_SYSTEM_TYPE_TABLET))
+	else if (CONFIG(SYSTEM_TYPE_DETACHABLE) ||
+		 CONFIG(SYSTEM_TYPE_TABLET))
 		fadt->preferred_pm_profile = PM_TABLET;
 	else
 		fadt->preferred_pm_profile = PM_DESKTOP;
@@ -1256,7 +1256,7 @@ unsigned long write_acpi_tables(unsigned long start)
 		acpi_add_table(rsdp, mcfg);
 	}
 
-	if (IS_ENABLED(CONFIG_TPM1)) {
+	if (CONFIG(TPM1)) {
 		printk(BIOS_DEBUG, "ACPI:    * TCPA\n");
 		tcpa = (acpi_tcpa_t *) current;
 		acpi_create_tcpa(tcpa);
@@ -1267,7 +1267,7 @@ unsigned long write_acpi_tables(unsigned long start)
 		}
 	}
 
-	if (IS_ENABLED(CONFIG_TPM2)) {
+	if (CONFIG(TPM2)) {
 		printk(BIOS_DEBUG, "ACPI:    * TPM2\n");
 		tpm2 = (acpi_tpm2_t *) current;
 		acpi_create_tpm2(tpm2);

src/arch/x86/acpi_device.c

@@ -19,7 +19,7 @@
 #include <arch/acpigen.h>
 #include <device/device.h>
 #include <device/path.h>
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
 #include <gpio.h>
 #endif
 
@@ -342,7 +342,7 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio)
 	/* Pin Table, one word for each pin */
 	for (pin = 0; pin < gpio->pin_count; pin++) {
 		uint16_t acpi_pin = gpio->pins[pin];
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
 		acpi_pin = gpio_acpi_pin(acpi_pin);
 #endif
 		acpigen_emit_word(acpi_pin);
@@ -352,7 +352,7 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio)
 	acpi_device_fill_from_len(resource_offset, start);
 
 	/* Resource Source Name String */
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
 	acpigen_emit_string(gpio->resource ? : gpio_acpi_path(gpio->pins[0]));
 #else
 	acpigen_emit_string(gpio->resource);

src/arch/x86/acpi_s3.c

@@ -82,7 +82,7 @@ static int backup_create_or_update(struct resume_backup *backup_mem,
 {
 	uintptr_t top;
 
-	if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) {
+	if (CONFIG(ACPI_HUGE_LOWMEM_BACKUP)) {
 		base = CONFIG_RAMBASE;
 		size = HIGH_MEMORY_SAVE;
 	}
@@ -169,7 +169,7 @@ void acpi_prepare_resume_backup(void)
 	if (!acpi_s3_resume_allowed())
 		return;
 
-	if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE))
+	if (CONFIG(RELOCATABLE_RAMSTAGE))
 		return;
 
 	backup_create_or_update(NULL, (uintptr_t)_program,
@@ -194,7 +194,7 @@ static void acpi_jump_to_wakeup(void *vector)
 		return;
 	}
 
-	if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) {
+	if (!CONFIG(RELOCATABLE_RAMSTAGE)) {
 		struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME);
 		if (backup_mem && backup_mem->valid) {
 			backup_mem->valid = 0;
@@ -224,7 +224,7 @@ void __weak mainboard_suspend_resume(void)
 
 void acpi_resume(void *wake_vec)
 {
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+	if (CONFIG(HAVE_SMI_HANDLER)) {
 		void *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS);
 
 		/* Restore GNVS pointer in SMM if found */

src/arch/x86/assembly_entry.S

@@ -16,7 +16,7 @@
 
 #include <rules.h>
 
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 
 /*
  * This path is for stages that are post bootblock when employing
@@ -43,8 +43,8 @@ _start:
 	sub	%edi, %ecx
 	rep	stosl
 
-#if ((ENV_VERSTAGE && IS_ENABLED(CONFIG_VERSTAGE_DEBUG_SPINLOOP)) \
-	|| (ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_DEBUG_SPINLOOP)))
+#if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
+	|| (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP)))
 
 	/* Wait for a JTAG debugger to break in and set EBX non-zero */
 	xor	%ebx, %ebx
@@ -55,7 +55,7 @@ debug_spinloop:
 #endif
 
 	andl	$0xfffffff0, %esp
-#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE)
+#if CONFIG(IDT_IN_EVERY_STAGE)
 	call	exception_init
 #endif
 	call	car_stage_entry
@@ -75,7 +75,7 @@ car_stage_entry:
 #include <arch/x86/prologue.inc>
 #include <cpu/x86/32bit/entry32.inc>
 #include <cpu/x86/fpu_enable.inc>
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
 #include <cpu/x86/sse_enable.inc>
 #endif
 

src/arch/x86/bootblock.ld

@@ -17,7 +17,7 @@
 #include <cpu/x86/16bit/entry16.ld>
 #include <cpu/x86/16bit/reset16.ld>
 #include <arch/x86/id.ld>
-#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
 #include <cpu/intel/fit/fit.ld>
 #endif
 

src/arch/x86/bootblock_crt0.S

@@ -32,7 +32,7 @@
 #include <cpu/x86/16bit/reset16.inc>
 #include <cpu/x86/32bit/entry32.inc>
 
-#if IS_ENABLED(CONFIG_BOOTBLOCK_DEBUG_SPINLOOP)
+#if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)
 
 	/* Wait for a JTAG debugger to break in and set EBX non-zero */
 	xor	%ebx, %ebx
@@ -44,7 +44,7 @@ debug_spinloop:
 
 bootblock_protected_mode_entry:
 
-#if !IS_ENABLED(CONFIG_USE_MARCH_586)
+#if !CONFIG(USE_MARCH_586)
 	/* MMX registers required here */
 
 	/* BIST result in eax */
@@ -57,12 +57,12 @@ bootblock_protected_mode_entry:
 	movd	%edx, %mm2
 #endif
 
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
 enable_sse:
 	mov	%cr4, %eax
 	or	$CR4_OSFXSR, %ax
 	mov	%eax, %cr4
-#endif /* IS_ENABLED(CONFIG_SSE) */
+#endif /* CONFIG(SSE) */
 
 	/* We're done. Now it's up to platform-specific code */
 	jmp	bootblock_pre_c_entry

src/arch/x86/bootblock_romcc.S

@@ -37,7 +37,7 @@
 
 #include <arch/x86/timestamp.inc>
 
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
 #include <cpu/x86/sse_enable.inc>
 #endif
 

src/arch/x86/bootblock_simple.c

@@ -22,12 +22,12 @@ static void main(unsigned long bist)
 		bootblock_mainboard_init();
 
 		sanitize_cmos();
-#if IS_ENABLED(CONFIG_CMOS_POST)
+#if CONFIG(CMOS_POST)
 		cmos_post_init();
 #endif
 	}
 
-#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)
+#if CONFIG(VBOOT_SEPARATE_VERSTAGE)
 	const char *target1 = "fallback/verstage";
 #else
 	const char *target1 = "fallback/romstage";

src/arch/x86/c_start.S

@@ -25,7 +25,7 @@
 _stack:
 .space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE
 _estack:
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
 .global thread_stacks
 thread_stacks:
 .space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS
@@ -76,7 +76,7 @@ _start:
 	movl	$_estack, %esp
 	andl	$(~(CONFIG_STACK_SIZE-1)), %esp
 
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
 	/* Push the thread pointer. */
 	push	$0
 #endif
@@ -93,7 +93,7 @@ _start:
 
 	andl	$0xFFFFFFF0, %esp
 
-#if IS_ENABLED(CONFIG_GDB_WAIT)
+#if CONFIG(GDB_WAIT)
 	call gdb_hw_init
 	call gdb_stub_breakpoint
 #endif
@@ -104,7 +104,7 @@ _start:
 	hlt
 	jmp	.Lhlt
 
-#if IS_ENABLED(CONFIG_GDB_WAIT)
+#if CONFIG(GDB_WAIT)
 
 	.globl gdb_stub_breakpoint
 gdb_stub_breakpoint:

src/arch/x86/car.ld

@@ -19,7 +19,7 @@
 . = CONFIG_DCACHE_RAM_BASE;
 .car.data . (NOLOAD) : {
 	_car_region_start = . ;
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
 	/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
 	 * aligned when using this option. */
 	_pagetables = . ;
@@ -28,7 +28,7 @@
 #endif
 	/* Vboot work buffer only needs to be available when verified boot
 	 * starts in bootblock. */
-#if IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)
+#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)
 	VBOOT2_WORK(., 16K)
 #endif
 	/* Vboot measured boot TCPA log measurements.
@@ -38,7 +38,7 @@
 	/* Stack for CAR stages. Since it persists across all stages that
 	 * use CAR it can be reused. The chipset/SoC is expected to provide
 	 * the stack size. */
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 	_car_stack_start = .;
 	. += CONFIG_DCACHE_BSP_STACK_SIZE;
 	_car_stack_end = .;
@@ -48,7 +48,7 @@
          * multiple stages (romstage and verstage) have a consistent
          * link address of these shared objects. */
 	PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
 	. = ALIGN(32);
 	/* Page directory pointer table resides here. There are 4 8-byte entries
 	 * totalling 32 bytes that need to be 32-byte aligned. The reason the
@@ -74,7 +74,7 @@
 	 * cbmem console. This is useful for clearing this area on a per-stage
 	 * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
 	_car_global_start = .;
-#if IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
+#if CONFIG(NO_CAR_GLOBAL_MIGRATION)
 	/* Allow global unitialized variables when CAR_GLOBALs are not used. */
 	*(.bss)
 	*(.bss.*)
@@ -89,15 +89,15 @@
 	_car_global_end = .;
 	_car_relocatable_data_end = .;
 
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) && \
-    !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && \
+    !CONFIG(USE_NATIVE_RAMINIT)
 	. = ABSOLUTE(0xff7e1000);
 	_mrc_pool = .;
 	. += 0x5000;
 	_emrc_pool = .;
 #endif
 
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 	_car_stack_start = .;
 	_car_stack_end = _car_region_end;
 #endif
@@ -113,7 +113,7 @@
 .illegal_globals . : {
 	*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
 		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-#if !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
+#if !CONFIG(NO_CAR_GLOBAL_MIGRATION)
 	*(.bss)
 	*(.bss.*)
 	*(.sbss)
@@ -125,9 +125,9 @@
 }
 
 _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
 _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
 #endif
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
 #endif

src/arch/x86/cbmem.c

@@ -15,7 +15,7 @@
 #include <cbmem.h>
 #include <arch/acpi.h>
 
-#if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP)
+#if CONFIG(CBMEM_TOP_BACKUP)
 
 void *cbmem_top(void)
 {
@@ -39,7 +39,7 @@ void *cbmem_top(void)
 /* Something went wrong, our high memory area got wiped */
 void cbmem_fail_resume(void)
 {
-#if !defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if !defined(__PRE_RAM__) && CONFIG(HAVE_ACPI_RESUME)
 	/* ACPI resume needs to be cleared in the fail-to-recover case, but that
 	 * condition is only handled during ramstage. */
 	acpi_fail_wakeup();

src/arch/x86/cpu.c

@@ -284,7 +284,7 @@ void lb_arch_add_records(struct lb_header *header)
 	struct lb_tsc_info *tsc_info;
 
 	/* Don't advertise a TSC rate unless it's constant. */
-	if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+	if (!CONFIG(TSC_CONSTANT_RATE))
 		return;
 
 	freq_khz = tsc_freq_mhz() * 1000;
@@ -302,7 +302,7 @@ void lb_arch_add_records(struct lb_header *header)
 void arch_bootstate_coreboot_exit(void)
 {
 	/* APs are already parked by existing infrastructure. */
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK))
+	if (!CONFIG(PARALLEL_MP_AP_WORK))
 		return;
 
 	/* APs are waiting for work. Last thing to do is park them. */

src/arch/x86/exception.c

@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#if IS_ENABLED(CONFIG_GDB_STUB)
+#if CONFIG(GDB_STUB)
 
 /* BUFMAX defines the maximum number of characters in inbound/outbound buffers.
  * At least NUM_REGBYTES*2 are needed for register packets
@@ -394,7 +394,7 @@ void x86_exception(struct eregs *info);
 
 void x86_exception(struct eregs *info)
 {
-#if IS_ENABLED(CONFIG_GDB_STUB)
+#if CONFIG(GDB_STUB)
 	int signo;
 	memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t));
 	gdb_stub_registers[PC] = info->eip;

src/arch/x86/exit_car.S

@@ -61,7 +61,7 @@ _start:
 	 *   0x00: Number of variable MTRRs to clear
 	 */
 
-#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
+#if CONFIG(SOC_SETS_MSRS)
 
 	mov	%esp, %ebp
 	/* Need to align stack to 16 bytes at the call instruction. Therefore

src/arch/x86/gdt.c

@@ -40,7 +40,7 @@ static void move_gdt(int is_recovery)
 	struct gdtarg gdtarg;
 
 	/* ramstage is already in high memory. No need to use a new gdt. */
-	if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE))
+	if (CONFIG(RELOCATABLE_RAMSTAGE))
 		return;
 
 	newgdt = cbmem_find(CBMEM_ID_GDT);

src/arch/x86/include/arch/acpi.h

@@ -32,7 +32,7 @@
  * The type and enable fields are common in ACPI, but the
  * values themselves are hardware implementation defined.
  */
-#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES)
+#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES)
  #define SLP_EN		(1 << 13)
  #define SLP_TYP_SHIFT	10
  #define SLP_TYP	(7 << SLP_TYP_SHIFT)
@@ -41,7 +41,7 @@
  #define  SLP_TYP_S3	5
  #define  SLP_TYP_S4	6
  #define  SLP_TYP_S5	7
-#elif IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES)
+#elif CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES)
  #define SLP_EN		(1 << 13)
  #define SLP_TYP_SHIFT	10
  #define SLP_TYP	(7 << SLP_TYP_SHIFT)
@@ -776,7 +776,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current);
 void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id);
 void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length);
 void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt);
-#if IS_ENABLED(CONFIG_COMMON_FADT)
+#if CONFIG(COMMON_FADT)
 void acpi_fill_fadt(acpi_fadt_t *fadt);
 #endif
 
@@ -885,8 +885,8 @@ enum {
 	ACPI_S5,
 };
 
-#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES) \
-		|| IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES)
+#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \
+		|| CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES)
 /* Given the provided PM1 control register return the ACPI sleep type. */
 static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt)
 {
@@ -909,7 +909,7 @@ int acpi_get_gpe(int gpe);
 
 static inline int acpi_s3_resume_allowed(void)
 {
-	return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME);
+	return CONFIG(HAVE_ACPI_RESUME);
 }
 
 /* Return address in reserved memory where to backup low memory
@@ -919,7 +919,7 @@ static inline int acpi_s3_resume_allowed(void)
  */
 void *acpi_backup_container(uintptr_t base, size_t size);
 
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
 
 #ifdef __PRE_RAM__
 static inline int acpi_is_wakeup_s3(void)

src/arch/x86/include/arch/cpu.h

@@ -188,7 +188,7 @@ struct thread;
 struct cpu_info {
 	struct device *cpu;
 	unsigned int index;
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
 	struct thread *thread;
 #endif
 };

src/arch/x86/include/arch/early_variables.h

@@ -19,7 +19,7 @@
 #include <arch/symbols.h>
 #include <stdlib.h>
 
-#if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
+#if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION)
 asm(".section .car.global_data,\"w\",@nobits");
 asm(".previous");
 #ifdef __clang__
@@ -100,6 +100,6 @@ static inline int car_active(void) { return 0; }
 #define car_get_var(var) (var)
 #define car_sync_var(var) (var)
 #define car_set_var(var, val)	(var) = (val)
-#endif /* ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) */
+#endif /* ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) */
 
 #endif /* ARCH_EARLY_VARIABLES_H */

src/arch/x86/include/arch/exception.h

@@ -32,7 +32,7 @@
 
 #include <arch/cpu.h>
 
-#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
+#if CONFIG(IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
 asmlinkage void exception_init(void);
 #else
 static inline void exception_init(void) { /* not implemented */ }

src/arch/x86/include/arch/interrupt.h

@@ -21,9 +21,9 @@
 #include "registers.h"
 
 /* setup interrupt handlers for mainboard */
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
+#if CONFIG(PCI_OPTION_ROM_RUN_REALMODE)
 extern void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void));
-#elif IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
+#elif CONFIG(PCI_OPTION_ROM_RUN_YABEL)
 #include <device/oprom/yabel/biosemu.h>
 #else
 static inline void mainboard_interrupt_handlers(int intXX,

src/arch/x86/include/arch/pci_io_cfg.h

@@ -21,7 +21,7 @@
 static __always_inline
 unsigned int pci_io_encode_addr(pci_devfn_t dev, unsigned int where)
 {
-	if (IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)) {
+	if (CONFIG(PCI_IO_CFG_EXT)) {
 		// seg == 0
 		return dev >> 4 | (where & 0xff) | ((where & 0xf00) << 16);
 	} else {
@@ -77,7 +77,7 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
 	outl(value, 0xCFC);
 }
 
-#if !IS_ENABLED(CONFIG_MMCONF_SUPPORT)
+#if !CONFIG(MMCONF_SUPPORT)
 
 /* Avoid name collisions as different stages have different signature
  * for these functions. The _s_ stands for simple, fundamental IO or

src/arch/x86/include/arch/registers.h

@@ -60,7 +60,7 @@ struct eregs {
 };
 #endif // !ASSEMBLER
 
-#if IS_ENABLED(CONFIG_COMPILER_LLVM_CLANG)
+#if CONFIG(COMPILER_LLVM_CLANG)
 #define ADDR32(opcode) opcode
 #else
 #define ADDR32(opcode) addr32 opcode

src/arch/x86/include/arch/smp/spinlock.h

@@ -15,9 +15,9 @@
 #define ARCH_SMP_SPINLOCK_H
 
 #if !defined(__PRE_RAM__) \
-	|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)	\
-	|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)	\
-	|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+	|| CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)	\
+	|| CONFIG(HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)	\
+	|| CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
 
 /*
  * Your basic SMP spinlocks, allowing only a single CPU anywhere

src/arch/x86/include/cf9_reset.h

@@ -27,7 +27,7 @@ void do_system_reset(void);
 void do_full_reset(void);
 
 /* Called by functions below before reset. */
-#if IS_ENABLED(CONFIG_HAVE_CF9_RESET_PREPARE)
+#if CONFIG(HAVE_CF9_RESET_PREPARE)
 void cf9_reset_prepare(void);
 #else
 static inline void cf9_reset_prepare(void) {}

src/arch/x86/ioapic.c

@@ -103,7 +103,7 @@ static void load_vectors(void *ioapic_base)
 
 	ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
 
-	if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_FSB)) {
+	if (CONFIG(IOAPIC_INTERRUPTS_ON_FSB)) {
 		/*
 		 * For the Pentium 4 and above APICs deliver their interrupts
 		 * on the front side bus, enable that.
@@ -111,7 +111,7 @@ static void load_vectors(void *ioapic_base)
 		printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
 		io_apic_write(ioapic_base, 0x03,
 			      io_apic_read(ioapic_base, 0x03) | (1 << 0));
-	} else if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) {
+	} else if (CONFIG(IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) {
 		printk(BIOS_DEBUG,
 			"IOAPIC: Enabling interrupts on APIC serial bus\n");
 		io_apic_write(ioapic_base, 0x03, 0);

src/arch/x86/memlayout.ld

@@ -62,7 +62,7 @@ SECTIONS
 #include <cpu/x86/16bit/entry16.ld>
 #include <cpu/x86/16bit/reset16.ld>
 #include <arch/x86/id.ld>
-#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
 #include <cpu/intel/fit/fit.ld>
 #endif
 #endif  /* ENV_BOOTBLOCK */

src/arch/x86/pci_ops_conf1.c

@@ -18,7 +18,7 @@
  * Functions for accessing PCI configuration space with type 1 accesses
  */
 
-#if !IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)
+#if !CONFIG(PCI_IO_CFG_EXT)
 #define CONF_CMD(dev, where)	(0x80000000 | ((dev)->bus->secondary << 16) | \
 					((dev)->path.pci.devfn << 8) | (where & ~3))
 #else

src/arch/x86/pirq_routing.c

@@ -198,9 +198,9 @@ unsigned long copy_pirq_routing_table(unsigned long addr,
 		addr);
 	memcpy((void *)addr, routing_table, routing_table->size);
 	printk(BIOS_INFO, "done.\n");
-	if (IS_ENABLED(CONFIG_DEBUG_PIRQ))
+	if (CONFIG(DEBUG_PIRQ))
 		verify_copy_pirq_routing_table(addr, routing_table);
-	if (IS_ENABLED(CONFIG_PIRQ_ROUTE))
+	if (CONFIG(PIRQ_ROUTE))
 		pirq_route_irqs(addr);
 
 	return addr + routing_table->size;

src/arch/x86/postcar_loader.c

@@ -106,7 +106,7 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf,
 
 void postcar_frame_add_romcache(struct postcar_frame *pcf, int type)
 {
-	if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
+	if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED))
 		return;
 	postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type);
 }
@@ -151,7 +151,7 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf)
 
 	finalize_load(rsl.params, pcf->stack);
 
-	if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE))
+	if (!CONFIG(NO_STAGE_CACHE))
 		stage_cache_add(STAGE_POSTCAR, prog);
 }
 
@@ -162,7 +162,7 @@ void run_postcar_phase(struct postcar_frame *pcf)
 
 	postcar_commit_mtrrs(pcf);
 
-	if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE) &&
+	if (!CONFIG(NO_STAGE_CACHE) &&
 				romstage_handoff_is_resume()) {
 		stage_cache_load_stage(STAGE_POSTCAR, &prog);
 		/* This is here to allow platforms to pass different stack

src/arch/x86/smbios.c

@@ -30,7 +30,7 @@
 #include <memory_info.h>
 #include <spd.h>
 #include <cbmem.h>
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
 #include <vendorcode/google/chromeos/gnvs.h>
 #endif
 
@@ -350,7 +350,7 @@ static int smbios_write_type0(unsigned long *current, int handle)
 	t->length = len - 2;
 
 	t->vendor = smbios_add_string(t->eos, "coreboot");
-#if !IS_ENABLED(CONFIG_CHROMEOS)
+#if !CONFIG(CHROMEOS)
 	t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
 
 	t->bios_version = smbios_add_string(t->eos,
@@ -359,12 +359,12 @@ static int smbios_write_type0(unsigned long *current, int handle)
 #define SPACES \
 	"                                                                  "
 	t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	u32 version_offset = (u32)smbios_string_table_len(t->eos);
 #endif
 	t->bios_version = smbios_add_string(t->eos, SPACES);
 
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	/* SMBIOS offsets start at 1 rather than 0 */
 	chromeos_get_chromeos_acpi()->vbt10 =
 		(u32)t->eos + (version_offset - 1);
@@ -390,10 +390,10 @@ static int smbios_write_type0(unsigned long *current, int handle)
 		BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
 		BIOS_CHARACTERISTICS_UPGRADEABLE;
 
-	if (IS_ENABLED(CONFIG_CARDBUS_PLUGIN_SUPPORT))
+	if (CONFIG(CARDBUS_PLUGIN_SUPPORT))
 		t->bios_characteristics |= BIOS_CHARACTERISTICS_PC_CARD;
 
-	if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
+	if (CONFIG(HAVE_ACPI_TABLES))
 		t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI;
 
 	t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET;
@@ -402,7 +402,7 @@ static int smbios_write_type0(unsigned long *current, int handle)
 	return len;
 }
 
-#if !IS_ENABLED(CONFIG_SMBIOS_PROVIDED_BY_MOBO)
+#if !CONFIG(SMBIOS_PROVIDED_BY_MOBO)
 
 const char *__weak smbios_mainboard_serial_number(void)
 {
@@ -753,7 +753,7 @@ unsigned long smbios_write_tables(unsigned long current)
 		handle++));
 	update_max(len, max_struct_size, smbios_write_type11(&current,
 		&handle));
-	if (IS_ENABLED(CONFIG_ELOG))
+	if (CONFIG(ELOG))
 		update_max(len, max_struct_size,
 			elog_smbios_write_type15(&current,handle++));
 	update_max(len, max_struct_size, smbios_write_type17(&current,

src/arch/x86/tables.c

@@ -238,17 +238,17 @@ void arch_write_tables(uintptr_t coreboot_table)
 	unsigned long rom_table_end = 0xf0000;
 
 	/* This table must be between 0x0f0000 and 0x100000 */
-	if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE))
+	if (CONFIG(GENERATE_PIRQ_TABLE))
 		rom_table_end = write_pirq_table(rom_table_end);
 
 	/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
-	if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE))
+	if (CONFIG(GENERATE_MP_TABLE))
 		rom_table_end = write_mptable(rom_table_end);
 
-	if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
+	if (CONFIG(HAVE_ACPI_TABLES))
 		rom_table_end = write_acpi_table(rom_table_end);
 
-	if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES))
+	if (CONFIG(GENERATE_SMBIOS_TABLES))
 		rom_table_end = write_smbios_table(rom_table_end);
 
 	sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table);

src/arch/x86/timestamp.c

@@ -24,7 +24,7 @@ uint64_t timestamp_get(void)
 int timestamp_tick_freq_mhz(void)
 {
 	/* Chipsets that have a constant TSC provide this value correctly. */
-	if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+	if (CONFIG(TSC_CONSTANT_RATE))
 		return tsc_freq_mhz();
 
 	/* Filling tick_freq_mhz = 0 in timestamps-table will trigger

src/commonlib/cbfs.c

@@ -27,7 +27,7 @@
 #endif
 #if defined(IS_ENABLED)
 
-#if IS_ENABLED(CONFIG_DEBUG_CBFS)
+#if CONFIG(DEBUG_CBFS)
 #define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x)
 #else
 #define DEBUG(x...)

src/commonlib/include/commonlib/stdlib.h

@@ -35,7 +35,7 @@
 #include <stdlib.h>
 #include <string.h>
 
-#if IS_ENABLED(CONFIG_COREBOOT_BUILD)
+#if CONFIG(COREBOOT_BUILD)
 #include <console/console.h>
 #include <halt.h>
 #define printf(...)		printk(BIOS_ERR, __VA_ARGS__)

src/commonlib/storage/mmc.c

@@ -127,7 +127,7 @@ int mmc_send_ext_csd(struct sd_mmc_ctrlr *ctrlr, unsigned char *ext_csd)
 
 	rv = ctrlr->send_cmd(ctrlr, &cmd, &data);
 
-	if (!rv && IS_ENABLED(CONFIG_SD_MMC_TRACE)) {
+	if (!rv && CONFIG(SD_MMC_TRACE)) {
 		int i, size;
 
 		size = data.blocks * data.blocksize;

src/commonlib/storage/sd_mmc.c

@@ -168,7 +168,7 @@ int sd_mmc_enter_standby(struct storage_media *media)
 
 	/* Test for SD version 2 */
 	err = CARD_TIMEOUT;
-	if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD)) {
+	if (CONFIG(COMMONLIB_STORAGE_SD)) {
 		err = sd_send_if_cond(media);
 
 		/* Get SD card operating condition */
@@ -177,7 +177,7 @@ int sd_mmc_enter_standby(struct storage_media *media)
 	}
 
 	/* If the command timed out, we check for an MMC card */
-	if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC) && (err == CARD_TIMEOUT)) {
+	if (CONFIG(COMMONLIB_STORAGE_MMC) && (err == CARD_TIMEOUT)) {
 		/* Some cards seem to need this */
 		sd_mmc_go_idle(media);
 

src/commonlib/storage/sd_mmc.h

@@ -75,12 +75,12 @@ int sd_set_partition(struct storage_media *media,
 /* Controller debug functions */
 #define sdhc_debug(format...) \
 	do {						\
-		if (IS_ENABLED(CONFIG_SDHC_DEBUG))	\
+		if (CONFIG(SDHC_DEBUG))	\
 			printk(BIOS_DEBUG, format);	\
 	} while (0)
 #define sdhc_trace(format...) \
 	do {						\
-		if (IS_ENABLED(CONFIG_SDHC_TRACE))	\
+		if (CONFIG(SDHC_TRACE))	\
 			printk(BIOS_DEBUG, format);	\
 	} while (0)
 #define sdhc_error(format...) printk(BIOS_ERR, "ERROR: " format)
@@ -88,12 +88,12 @@ int sd_set_partition(struct storage_media *media,
 /* Card/device debug functions */
 #define sd_mmc_debug(format...) \
 	do {						\
-		if (IS_ENABLED(CONFIG_SD_MMC_DEBUG))	\
+		if (CONFIG(SD_MMC_DEBUG))	\
 			printk(BIOS_DEBUG, format);	\
 	} while (0)
 #define sd_mmc_trace(format...) \
 	do {						\
-		if (IS_ENABLED(CONFIG_SD_MMC_TRACE))	\
+		if (CONFIG(SD_MMC_TRACE))	\
 			printk(BIOS_DEBUG, format);	\
 	} while (0)
 #define sd_mmc_error(format...) printk(BIOS_ERR, "ERROR: " format)

src/commonlib/storage/sdhci.c

@@ -318,7 +318,7 @@ static int sdhci_send_command(struct sd_mmc_ctrlr *ctrlr,
 
 	sdhc_log_command(cmd);
 
-	if (IS_ENABLED(CONFIG_SDHCI_BOUNCE_BUFFER) && data) {
+	if (CONFIG(SDHCI_BOUNCE_BUFFER) && data) {
 		if (data->flags & DATA_FLAG_READ) {
 			buf = data->dest;
 			bbflags = GEN_BB_WRITE;
@@ -348,7 +348,7 @@ static int sdhci_send_command(struct sd_mmc_ctrlr *ctrlr,
 	sdhci_led_control(ctrlr, 0);
 	sdhc_log_ret(ret);
 
-	if (IS_ENABLED(CONFIG_SDHCI_BOUNCE_BUFFER) && bbstate)
+	if (CONFIG(SDHCI_BOUNCE_BUFFER) && bbstate)
 		bounce_buffer_stop(bbstate);
 
 	return ret;
@@ -594,7 +594,7 @@ static void sdhci_set_ios(struct sd_mmc_ctrlr *ctrlr)
 	}
 
 	/* Set the new bus width */
-	if (IS_ENABLED(CONFIG_SDHC_DEBUG)
+	if (CONFIG(SDHC_DEBUG)
 		&& ((ctrl ^ previous_ctrl) & (SDHCI_CTRL_4BITBUS
 		| ((version >= SDHCI_SPEC_300) ? SDHCI_CTRL_8BITBUS : 0))))
 		sdhc_debug("SDHCI bus width: %d bit%s\n", bus_width,

src/commonlib/storage/sdhci_display.c

@@ -26,7 +26,7 @@
 
 static void sdhci_display_bus_width(struct sdhci_ctrlr *sdhci_ctrlr)
 {
-	if (IS_ENABLED(CONFIG_SDHC_DEBUG)) {
+	if (CONFIG(SDHC_DEBUG)) {
 		int bits;
 		uint8_t host_ctrl;
 		uint16_t host2;
@@ -53,7 +53,7 @@ static void sdhci_display_bus_width(struct sdhci_ctrlr *sdhci_ctrlr)
 
 static void sdhci_display_clock(struct sdhci_ctrlr *sdhci_ctrlr)
 {
-	if (IS_ENABLED(CONFIG_SDHC_DEBUG)) {
+	if (CONFIG(SDHC_DEBUG)) {
 		uint16_t clk_ctrl;
 		uint32_t clock;
 		uint32_t divisor;
@@ -79,7 +79,7 @@ static void sdhci_display_clock(struct sdhci_ctrlr *sdhci_ctrlr)
 
 static void sdhci_display_voltage(struct sdhci_ctrlr *sdhci_ctrlr)
 {
-	if (IS_ENABLED(CONFIG_SDHC_DEBUG)) {
+	if (CONFIG(SDHC_DEBUG)) {
 		u8 pwr_ctrl;
 		const char *voltage;
 		const char *voltage_table[8] = {

src/commonlib/storage/storage.c

@@ -70,7 +70,7 @@ static void display_capacity(struct storage_media *media, int partition_number)
 	capacity = media->capacity[partition_number];
 	name = storage_partition_name(media, partition_number);
 	separator = "";
-	if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC) && !IS_SD(media))
+	if (CONFIG(COMMONLIB_STORAGE_MMC) && !IS_SD(media))
 		separator = ": ";
 
 	/* Determine the decimal divisor for the capacity */
@@ -124,7 +124,7 @@ void storage_display_setup(struct storage_media *media)
 		* media->write_bl_len);
 
 	/* Display the partition capacities */
-	if (IS_ENABLED(CONFIG_SDHC_DEBUG)) {
+	if (CONFIG(SDHC_DEBUG)) {
 		for (partition_number = 0; partition_number
 			< ARRAY_SIZE(media->capacity); partition_number++) {
 			if (!media->capacity[partition_number])
@@ -175,9 +175,9 @@ int storage_startup(struct storage_media *media)
 		return err;
 
 	/* Increase the bus frequency */
-	if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media))
+	if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media))
 		err = sd_change_freq(media);
-	else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC)) {
+	else if (CONFIG(COMMONLIB_STORAGE_MMC)) {
 		err = mmc_change_freq(media);
 		if (!err)
 			mmc_update_capacity(media);
@@ -189,9 +189,9 @@ int storage_startup(struct storage_media *media)
 	media->caps &= ctrlr->caps;
 
 	/* Increase the bus width if possible */
-	if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media))
+	if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media))
 		err = sd_set_bus_width(media);
-	else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC))
+	else if (CONFIG(COMMONLIB_STORAGE_MMC))
 		err = mmc_set_bus_width(media);
 	if (err)
 		return err;
@@ -329,9 +329,9 @@ int storage_set_partition(struct storage_media *media,
 
 	/* Select the partition */
 	err = -1;
-	if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media))
+	if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media))
 		err = sd_set_partition(media, partition_number);
-	else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC))
+	else if (CONFIG(COMMONLIB_STORAGE_MMC))
 		err = mmc_set_partition(media, partition_number);
 	if (err)
 		sd_mmc_error("Invalid partition number!\n");
@@ -345,9 +345,9 @@ const char *storage_partition_name(struct storage_media *media,
 
 	/* Get the partition name */
 	name = NULL;
-	if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media))
+	if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media))
 		name = sd_partition_name(media, partition_number);
-	else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC))
+	else if (CONFIG(COMMONLIB_STORAGE_MMC))
 		name = mmc_partition_name(media, partition_number);
 	return name;
 }

src/console/console.c

@@ -79,7 +79,7 @@ void console_write_line(uint8_t *buffer, size_t number_of_bytes)
 }
 
 
-#if IS_ENABLED(CONFIG_GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
+#if CONFIG(GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
 void gdb_hw_init(void)
 {
 	__gdb_hw_init();

src/console/init.c

@@ -73,7 +73,7 @@ int console_log_level(int msg_level)
 	if (msg_level <= log_level)
 		return CONSOLE_LOG_ALL;
 
-	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM) && (msg_level <= BIOS_DEBUG))
+	if (CONFIG(CONSOLE_CBMEM) && (msg_level <= BIOS_DEBUG))
 		return CONSOLE_LOG_FAST;
 
 	return 0;
@@ -83,10 +83,10 @@ asmlinkage void console_init(void)
 {
 	init_log_level();
 
-	if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT))
+	if (CONFIG(DEBUG_CONSOLE_INIT))
 		car_set_var(console_inited, 1);
 
-	if (IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE)
+	if (CONFIG(EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE)
 		pci_early_bridge_init();
 
 	console_hw_init();

src/console/post.c

@@ -20,7 +20,7 @@
 #include <device/device.h>
 #include <pc80/mc146818rtc.h>
 #include <smp/spinlock.h>
-#if IS_ENABLED(CONFIG_POST_IO)
+#if CONFIG(POST_IO)
 #include <arch/io.h>
 #endif
 
@@ -40,7 +40,7 @@ void __weak mainboard_post(uint8_t value)
 #define mainboard_post(x)
 #endif
 
-#if IS_ENABLED(CONFIG_CMOS_POST)
+#if CONFIG(CMOS_POST)
 
 DECLARE_SPIN_LOCK(cmos_post_lock)
 
@@ -48,7 +48,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock)
 void cmos_post_log(void)
 {
 	u8 code = 0;
-#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
+#if CONFIG(CMOS_POST_EXTRA)
 	u32 extra = 0;
 #endif
 
@@ -58,13 +58,13 @@ void cmos_post_log(void)
 	switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
 	case CMOS_POST_BANK_0_MAGIC:
 		code = cmos_read(CMOS_POST_BANK_1_OFFSET);
-#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
+#if CONFIG(CMOS_POST_EXTRA)
 		extra = cmos_read32(CMOS_POST_BANK_1_EXTRA);
 #endif
 		break;
 	case CMOS_POST_BANK_1_MAGIC:
 		code = cmos_read(CMOS_POST_BANK_0_OFFSET);
-#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
+#if CONFIG(CMOS_POST_EXTRA)
 		extra = cmos_read32(CMOS_POST_BANK_0_EXTRA);
 #endif
 		break;
@@ -82,9 +82,9 @@ void cmos_post_log(void)
 	default:
 		printk(BIOS_WARNING, "POST: Unexpected post code "
 		       "in previous boot: 0x%02x\n", code);
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
 		elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code);
-#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
+#if CONFIG(CMOS_POST_EXTRA)
 		if (extra)
 			elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra);
 #endif
@@ -92,7 +92,7 @@ void cmos_post_log(void)
 	}
 }
 
-#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
+#if CONFIG(CMOS_POST_EXTRA)
 void post_log_extra(u32 value)
 {
 	spin_lock(&cmos_post_lock);
@@ -146,14 +146,14 @@ static void cmos_post_code(u8 value)
 
 void post_code(uint8_t value)
 {
-#if !IS_ENABLED(CONFIG_NO_POST)
-#if IS_ENABLED(CONFIG_CONSOLE_POST)
+#if !CONFIG(NO_POST)
+#if CONFIG(CONSOLE_POST)
 	printk(BIOS_EMERG, "POST: 0x%02x\n", value);
 #endif
-#if IS_ENABLED(CONFIG_CMOS_POST)
+#if CONFIG(CMOS_POST)
 	cmos_post_code(value);
 #endif
-#if IS_ENABLED(CONFIG_POST_IO)
+#if CONFIG(POST_IO)
 	outb(value, CONFIG_POST_IO_PORT);
 #endif
 #endif

src/console/printk.c

@@ -26,7 +26,7 @@
 #include <stddef.h>
 #include <trace.h>
 
-#if (!defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
+#if (!defined(__PRE_RAM__) && CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
 DECLARE_SPIN_LOCK(console_lock)
 #endif
 
@@ -49,7 +49,7 @@ int vprintk(int msg_level, const char *fmt, va_list args)
 {
 	int i, log_this;
 
-	if (IS_ENABLED(CONFIG_SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM &&
+	if (CONFIG(SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM &&
 		!boot_cpu())
 		return 0;
 
@@ -59,7 +59,7 @@ int vprintk(int msg_level, const char *fmt, va_list args)
 
 	DISABLE_TRACE;
 #ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
 	spin_lock(romstage_console_lock());
 #endif
 #else
@@ -74,7 +74,7 @@ int vprintk(int msg_level, const char *fmt, va_list args)
 	}
 
 #ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
 	spin_unlock(romstage_console_lock());
 #endif
 #else

src/console/vtxprintf.c

@@ -20,7 +20,7 @@
 
 #define call_tx(x) tx_byte(x, data)
 
-#if !IS_ENABLED(CONFIG_ARCH_MIPS)
+#if !CONFIG(ARCH_MIPS)
 #define SUPPORT_64BIT_INTS
 #endif
 

src/cpu/amd/agesa/family12/model_12_init.c

@@ -34,7 +34,7 @@ static void model_12_init(struct device *dev)
 	msr_t msr;
 	int num_banks;
 
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
 #endif
 
@@ -65,7 +65,7 @@ static void model_12_init(struct device *dev)
 	/* Set the processor name string */
 	//  init_processor_name();
 
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 
 	if (siblings > 0) {

src/cpu/amd/agesa/family14/model_14_init.c

@@ -33,7 +33,7 @@ static void model_14_init(struct device *dev)
 	msr_t msr;
 	int num_banks;
 	int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
 #endif
 	printk(BIOS_DEBUG, "Model 14 Init.\n");
@@ -83,7 +83,7 @@ static void model_14_init(struct device *dev)
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 
 	if (siblings > 0) {

src/cpu/amd/agesa/family15tn/model_15_init.c

@@ -37,7 +37,7 @@ static void model_15_init(struct device *dev)
 	int num_banks;
 	int msrno;
 	unsigned int cpu_idx;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
 #endif
 
@@ -82,7 +82,7 @@ static void model_15_init(struct device *dev)
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 
 	if (siblings > 0) {
@@ -102,7 +102,7 @@ static void model_15_init(struct device *dev)
 	msr.hi &= ~(1 << (46 - 32));
 	wrmsr(NB_CFG_MSR, msr);
 
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+	if (CONFIG(HAVE_SMI_HANDLER)) {
 		cpu_idx = cpu_info()->index;
 		printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
 

src/cpu/amd/agesa/family16kb/model_16_init.c

@@ -35,7 +35,7 @@ static void model_16_init(struct device *dev)
 	msr_t msr;
 	int num_banks;
 	int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
 #endif
 
@@ -80,7 +80,7 @@ static void model_16_init(struct device *dev)
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 
 	if (siblings > 0) {

src/cpu/amd/car/cache_as_ram.inc

@@ -141,7 +141,7 @@ CAR_FAM10_out:
 
 CAR_FAM10_errata_applied:
 
-#if IS_ENABLED(CONFIG_MMCONF_SUPPORT)
+#if CONFIG(MMCONF_SUPPORT)
    #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
    #error "MMCONF_BASE_ADDRESS too big"
    #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
@@ -315,7 +315,7 @@ clear_fixed_var_mtrr_out:
 	 */
 .endm
 
-#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
+#if CONFIG(CPU_AMD_MODEL_10XXX)
   #if CacheSize > 0x80000
   #error Invalid CAR size, must be at most 128k (processor limit is 512k).
   #endif

src/cpu/amd/car/disable_cache_as_ram.c

@@ -80,7 +80,7 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
 
 	family = amd_fam1x_cpu_family();
 
-#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
+#if CONFIG(CPU_AMD_MODEL_10XXX)
 	if (family >= 0x6f) {
 		/* Family 15h or later */
 

src/cpu/amd/car/post_cache_as_ram.c

@@ -36,7 +36,7 @@
 	#error "You need to set CONFIG_RAMTOP greater than 1M"
 #endif
 
-#if IS_ENABLED(CONFIG_DEBUG_CAR)
+#if CONFIG(DEBUG_CAR)
 #define print_car_debug(format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg)
 #else
 #define print_car_debug(format, arg...)

src/cpu/amd/family_10h-family_15h/fidvid.c

@@ -95,21 +95,21 @@ b.-  prep_fid_change(...)
 
 static inline void print_debug_fv(const char *str, u32 val)
 {
-#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
+#if CONFIG(SET_FIDVID_DEBUG)
 	printk(BIOS_DEBUG, "%s%x\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_8(const char *str, u8 val)
 {
-#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
+#if CONFIG(SET_FIDVID_DEBUG)
 	printk(BIOS_DEBUG, "%s%02x\n", str, val);
 #endif
 }
 
 static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
 {
-#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
+#if CONFIG(SET_FIDVID_DEBUG)
 	printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
 #endif
 }
@@ -505,7 +505,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev,
 	}
 
 	   /* TODO: look into C1E state and F3xA0[IdleExitEn]*/
-	#if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)
+	#if CONFIG(SVI_HIGH_FREQ)
 	if (cpuRev & AMD_FAM10_C3) {
 		dword |= SVI_HIGH_FREQ_ON;
 	}
@@ -585,7 +585,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev,
 		if (cpuRev & AMD_DR_Bx ) {
 			smaf001 = 0xA6;
 		} else {
-		#if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)
+		#if CONFIG(SVI_HIGH_FREQ)
 			if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
 				smaf001 = 0xF6;
 			}
@@ -1036,7 +1036,7 @@ void init_fidvid_stage2(u32 apicid, u32 nodeid)
 }
 
 
-#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)
+#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST)
 struct ap_apicid_st {
 	u32 num;
 	// it could use 256 bytes for 64 node quad core system
@@ -1055,7 +1055,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp)
 
 int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
 {
-#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)
+#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST)
 	struct ap_apicid_st ap_apicidx;
 	u32 i;
 #endif
@@ -1070,8 +1070,8 @@ int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
 
 	print_debug_fv("BSP fid = ", fv.common_fid);
 
-#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \
-	!IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)
+#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \
+	!CONFIG(SET_FIDVID_CORE0_ONLY)
 	/* For all APs (We know the APIC ID of all APs even when the APIC ID
 	   is lifted) remote read from AP LAPIC_MSG_REG about max fid.
 	   Then calculate the common max fid that can be used for all

src/cpu/amd/family_10h-family_15h/init_cpus.c

@@ -18,7 +18,7 @@
 #include <device/pci_ops.h>
 #include "init_cpus.h"
 
-#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
+#if CONFIG(HAVE_OPTION_TABLE)
 #include "option_table.h"
 #endif
 #include <pc80/mc146818rtc.h>
@@ -30,17 +30,17 @@
 
 #include <southbridge/amd/common/reset.h>
 
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)
+#if CONFIG(SOUTHBRIDGE_AMD_SB700)
 #include <southbridge/amd/sb700/sb700.h>
 #endif
 
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
+#if CONFIG(SOUTHBRIDGE_AMD_SB800)
 #include <southbridge/amd/sb800/sb800.h>
 #endif
 
 #include "cpu/amd/car/disable_cache_as_ram.c"
 
-#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)
+#if CONFIG(PCI_IO_CFG_EXT)
 static void set_EnableCf8ExtCfg(void)
 {
 	// set the NB_CFG_MSR[46]=1;
@@ -156,7 +156,7 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
 	/* get_nodes define in ht_wrapper.c */
 	nodes = get_nodes();
 
-	if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) ||
+	if (!CONFIG(LOGICAL_CPUS) ||
 	    read_option(multi_core, 0) != 0) {	// 0 means multi core
 		disable_siblings = 1;
 	} else {
@@ -186,8 +186,8 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
 		for (j = jstart; j <= jend; j++) {
 			ap_apicid = get_boot_apic_id(i, j);
 
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
-#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
+#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
+#if !CONFIG(LIFT_BSP_APIC_ID)
 			if ((i != 0) || (j != 0))	/* except bsp */
 #endif
 				ap_apicid += CONFIG_APIC_ID_OFFSET;
@@ -231,7 +231,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
 	return result;
 }
 
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
 static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
 #endif
 
@@ -402,17 +402,17 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 		if (!is_fam15h())
 			set_apicid_cpuid_lo();
 		set_EnableCf8ExtCfg();
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)
+#if CONFIG(ENABLE_APIC_EXT_ID)
 		enable_apic_ext_id(id.nodeid);
 #endif
 	}
 
 	enable_lapic();
 
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
+#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
 	u32 initial_apicid = get_initial_apicid();
 
-#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
+#if !CONFIG(LIFT_BSP_APIC_ID)
 	if (initial_apicid != 0)	// other than bsp
 #endif
 	{
@@ -424,7 +424,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 
 		lapic_write(LAPIC_ID, dword);
 	}
-#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
+#if CONFIG(LIFT_BSP_APIC_ID)
 	bsp_apicid += CONFIG_APIC_ID_OFFSET;
 #endif
 
@@ -477,8 +477,8 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 			}
 		}
 
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)
+#if CONFIG(SET_FIDVID)
+#if CONFIG(LOGICAL_CPUS) && CONFIG(SET_FIDVID_CORE0_ONLY)
 		// Run on all AP for proper FID/VID setup.
 		if (id.coreid == 0)	// only need set fid for core0
 #endif
@@ -501,7 +501,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 		if (is_fam15h()) {
 			/* core 1 on node 0 is special; to avoid corrupting the
 			 * BSP do not alter MTRRs on that core */
-			if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+			if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
 				fam15_bsp_core1_apicid = CONFIG_APIC_ID_OFFSET + 1;
 			else
 				fam15_bsp_core1_apicid = 1;
@@ -578,7 +578,7 @@ static void start_node(u8 node)
 	/* Enable routing table */
 	printk(BIOS_DEBUG, "Start node %02x", node);
 
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
+#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
 	/* For FAM10 support, we need to set Dram base/limit for the new node */
 	pci_write_config32(NODE_MP(node), 0x44, 0);
 	pci_write_config32(NODE_MP(node), 0x40, 3);
@@ -1040,7 +1040,7 @@ void cpuSetAMDMSR(uint8_t node_id)
 		}
 	}
 
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
+#if CONFIG(SOUTHBRIDGE_AMD_SB700) || CONFIG(SOUTHBRIDGE_AMD_SB800)
 	if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
 		/* Set up message triggered C1E */
 		msr = rdmsr(MSR_INTPEND);
@@ -1060,7 +1060,7 @@ void cpuSetAMDMSR(uint8_t node_id)
 
 	if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) {
 		enable_c_states = 0;
-		if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
+		if (CONFIG(HAVE_ACPI_TABLES))
 			if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
 				enable_c_states = !!nvram;
 
@@ -1869,7 +1869,7 @@ void finalize_node_setup(struct sys_info *sysinfo)
 		cpuSetAMDPCI(i);
 	}
 
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
 	// Prep each node for FID/VID setup.
 	prep_fid_change();
 #endif
@@ -1883,6 +1883,6 @@ void finalize_node_setup(struct sys_info *sysinfo)
 #endif
 }
 
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
 # include "fidvid.c"
 #endif

src/cpu/amd/family_10h-family_15h/model_10xxx_init.c

@@ -62,7 +62,7 @@ static void model_10xxx_init(struct device *dev)
 	msr_t msr;
 	int num_banks;
 	struct node_core_id id;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
 #endif
 	uint8_t delay_start;
@@ -123,7 +123,7 @@ static void model_10xxx_init(struct device *dev)
 	/* Set the processor name string */
 	init_processor_name();
 
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 
 	if (siblings > 0) {
@@ -204,7 +204,7 @@ static void model_10xxx_init(struct device *dev)
 		wrmsr(BU_CFG2_MSR, msr);
 	}
 
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+	if (CONFIG(HAVE_SMI_HANDLER)) {
 		printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
 
 		/* Set SMM base address for this CPU */

src/cpu/amd/family_10h-family_15h/powernow_acpi.c

@@ -187,7 +187,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	uint8_t enable_c_states;
 
 	enable_c_states = 0;
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
 		enable_c_states = !!nvram;
 #endif

src/cpu/amd/family_10h-family_15h/ram_calc.c

@@ -44,7 +44,7 @@ static inline uint8_t is_fam15h(void)
 uint64_t get_uma_memory_size(uint64_t topmem)
 {
 	uint64_t uma_size = 0;
-	if (IS_ENABLED(CONFIG_GFXUMA)) {
+	if (CONFIG(GFXUMA)) {
 		/* refer to UMA Size Consideration in 780 BDG. */
 		if (topmem >= 0x40000000)	/* 1GB and above system memory */
 			uma_size = 0x10000000;	/* 256M recommended UMA */

src/cpu/amd/microcode/microcode.c

@@ -200,7 +200,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
 		}
 
 #ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
 		spin_lock(romstage_microcode_cbfs_lock());
 #endif
 #endif
@@ -210,7 +210,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
 		if (!ucode) {
 			UCODE_DEBUG("microcode file not found. Skipping updates.\n");
 #ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
 			spin_unlock(romstage_microcode_cbfs_lock());
 #endif
 #endif
@@ -220,7 +220,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
 		amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
 
 #ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
 		spin_unlock(romstage_microcode_cbfs_lock());
 #endif
 #endif

src/cpu/amd/pi/00630F01/fixme.c

@@ -88,7 +88,7 @@ void amd_initmmio(void)
 	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
 
-	if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
+	if (CONFIG(UDELAY_LAPIC)){
 		LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
 		MsrReg |= 1 << 11;
 		LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);

src/cpu/amd/pi/00630F01/model_15_init.c

@@ -36,7 +36,7 @@ static void model_15_init(struct device *dev)
 	int num_banks;
 	int msrno;
 	unsigned int cpu_idx;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
 #endif
 
@@ -78,7 +78,7 @@ static void model_15_init(struct device *dev)
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 
 	if (siblings > 0) {
@@ -98,7 +98,7 @@ static void model_15_init(struct device *dev)
 	msr.hi &= ~(1 << (46 - 32));
 	wrmsr(NB_CFG_MSR, msr);
 
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+	if (CONFIG(HAVE_SMI_HANDLER)) {
 		cpu_idx = cpu_info()->index;
 		printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
 

src/cpu/amd/pi/00660F01/fixme.c

@@ -94,7 +94,7 @@ void amd_initmmio(void)
 	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
 
-	if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
+	if (CONFIG(UDELAY_LAPIC)) {
 		LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
 		MsrReg |= 1 << 11;
 		LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);

src/cpu/amd/pi/00660F01/model_15_init.c

@@ -51,7 +51,7 @@ static void model_15_init(struct device *dev)
 	msr_t msr;
 	int num_banks;
 	int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
 #endif
 
@@ -90,7 +90,7 @@ static void model_15_init(struct device *dev)
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 
 	if (siblings > 0) {

src/cpu/amd/pi/00730F01/fixme.c

@@ -99,7 +99,7 @@ void amd_initmmio(void)
 	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
 
-	if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
+	if (CONFIG(UDELAY_LAPIC)) {
 		LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
 		MsrReg |= 1 << 11;
 		LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);

src/cpu/amd/pi/00730F01/model_16_init.c

@@ -34,7 +34,7 @@ static void model_16_init(struct device *dev)
 	msr_t msr;
 	int num_banks;
 	int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
 #endif
 
@@ -75,7 +75,7 @@ static void model_16_init(struct device *dev)
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	siblings = cpuid_ecx(0x80000008) & 0xff;
 
 	if (siblings > 0) {

src/cpu/amd/quadcore/quadcore.c

@@ -19,7 +19,7 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
-#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
+#if CONFIG(HAVE_OPTION_TABLE)
 #include "option_table.h"
 #endif
 
@@ -124,7 +124,7 @@ void real_start_other_core(uint32_t nodeid, uint32_t cores)
 	}
 }
 
-#if (!IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
+#if (!CONFIG(CPU_AMD_MODEL_10XXX))
 //it is running on core0 of node0
 static void start_other_cores(void)
 {

src/cpu/intel/car/non-evict/cache_as_ram.S

@@ -134,7 +134,7 @@ addrsize_set_high:
 	orl	$MTRR_DEF_TYPE_EN, %eax
 	wrmsr
 
-#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR)
+#if CONFIG(CPU_HAS_L2_ENABLE_MSR)
 	/*
 	 * Enable the L2 cache. Currently this assumes that this
 	 * only affect socketed CPU's for which this is always valid,
@@ -152,7 +152,7 @@ addrsize_set_high:
 	invd
 	movl	%eax, %cr0
 
-#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
+#if CONFIG(MICROCODE_UPDATE_PRE_RAM)
 update_microcode:
 	/* put the return address in %esp */
 	movl	$end_microcode_update, %esp

src/cpu/intel/car/p4-netburst/cache_as_ram.S

@@ -23,7 +23,7 @@
 
 /* Macro to access Local APIC registers at default base. */
 #define LAPIC(x)		$(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 /* Fixed location, ASSERTED in failover.ld if it changes. */
 .set ap_sipi_vector_in_rom, 0xff
 #endif
@@ -318,7 +318,7 @@ no_msr_11e:
 	invd
 	movl	%eax, %cr0
 
-#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
+#if CONFIG(MICROCODE_UPDATE_PRE_RAM)
 	update_microcode:
 	/* put the return address in %esp */
 	movl	$end_microcode_update, %esp

src/cpu/intel/car/romstage.c

@@ -54,7 +54,7 @@ static void romstage_main(unsigned long bist)
 	platform_enter_postcar();
 }
 
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 /* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
  * keeping changes in cache_as_ram.S easy to manage.
  */

src/cpu/intel/common/common_init.c

@@ -31,7 +31,7 @@ void set_feature_ctrl_vmx(void)
 {
 	msr_t msr;
 	uint32_t feature_flag;
-	int enable = IS_ENABLED(CONFIG_ENABLE_VMX);
+	int enable = CONFIG(ENABLE_VMX);
 
 	feature_flag = cpu_get_feature_flags_ecx();
 	/* Check that the VMX is supported before reading or writing the MSR. */
@@ -71,7 +71,7 @@ void set_feature_ctrl_vmx(void)
 void set_feature_ctrl_lock(void)
 {
 	msr_t msr;
-	int lock = IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT);
+	int lock = CONFIG(SET_IA32_FC_LOCK_BIT);
 	uint32_t feature_flag = cpu_get_feature_flags_ecx();
 
 	/* Check if VMX is supported before reading or writing the MSR */

src/cpu/intel/fsp_model_406dx/model_406dx_init.c

@@ -132,7 +132,7 @@ static void model_406dx_init(struct device *cpu)
 	x86_enable_cache();
 
 	/* Load microcode */
-	if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
+	if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
 		intel_update_microcode_from_cbfs();
 
 	/* Clear out pending MCEs */

src/cpu/intel/haswell/bootblock.c

@@ -23,7 +23,7 @@
 #include <cpu/intel/microcode/microcode.c>
 #include "haswell.h"
 
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)
+#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)
 /* Needed for RCBA access to set Soft Reset Data register */
 #include <southbridge/intel/lynxpoint/pch.h>
 #else

src/cpu/intel/haswell/romstage.c

@@ -30,7 +30,7 @@
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #endif
 #include <northbridge/intel/haswell/haswell.h>
@@ -89,7 +89,7 @@ void romstage_common(const struct romstage_params *params)
 	printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
 
 	if (wake_from_s3) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
 		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 #else
 		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
@@ -131,7 +131,7 @@ void romstage_common(const struct romstage_params *params)
 		/* Save data returned from MRC on non-S3 resumes. */
 		save_mrc_data(params->pei_data);
 	} else if (cbmem_initialize()) {
-	#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+	#if CONFIG(HAVE_ACPI_RESUME)
 		/* Failed S3 resume, reset to come up cleanly */
 		system_reset();
 	#endif

src/cpu/intel/hyperthreading/intel_sibling.c

@@ -19,7 +19,7 @@
 #include <smp/spinlock.h>
 #include <assert.h>
 
-#if IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)
+#if CONFIG(PARALLEL_CPU_INIT)
 #error Intel hyper-threading requires serialized CPU init
 #endif
 

src/cpu/intel/model_1067x/mp_init.c

@@ -75,7 +75,7 @@ static void per_cpu_smm_trigger(void)
 			printk(BIOS_DEBUG, "SMRR status: %senabled\n",
 			       ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
 		} else {
-			if (!IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT))
+			if (!CONFIG(SET_IA32_FC_LOCK_BIT))
 				printk(BIOS_INFO,
 				       "Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n");
 			ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);

src/cpu/intel/model_2065x/bootblock.c

@@ -23,7 +23,7 @@
 
 #include <cpu/intel/microcode/microcode.c>
 
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)
+#if CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK)
 #include <southbridge/intel/ibexpeak/pch.h>
 #include "model_2065x.h"
 #else

src/cpu/intel/model_206ax/bootblock.c

@@ -24,8 +24,8 @@
 #include <cpu/intel/microcode/microcode.c>
 #include "model_206ax.h"
 
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) || \
-	IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
+#if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \
+	CONFIG(SOUTHBRIDGE_INTEL_C216)
 /* Needed for RCBA access to set Soft Reset Data register */
 #include <southbridge/intel/bd82x6x/pch.h>
 #else

src/cpu/intel/model_f3x/model_f3x_init.c

@@ -24,7 +24,7 @@ static void model_f3x_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {
+	if (!CONFIG(PARALLEL_MP) && !intel_ht_sibling()) {
 		/* MTRRs are shared between threads */
 		x86_setup_mtrrs();
 		x86_mtrr_check();
@@ -37,7 +37,7 @@ static void model_f3x_init(struct device *cpu)
 	setup_lapic();
 
 	/* Start up my CPU siblings */
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+	if (!CONFIG(PARALLEL_MP))
 		intel_sibling_init(cpu);
 };
 

src/cpu/intel/smm/gen1/smmrelocate.c

@@ -175,7 +175,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 	}
 
 	/* Adjust available SMM handler memory size. */
-	if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
+	if (CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
 		ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE);
 		params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
 	}

src/cpu/intel/turbo/turbo.c

@@ -19,7 +19,7 @@
 #include <cpu/x86/msr.h>
 #include <arch/cpu.h>
 
-#if IS_ENABLED(CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED)
+#if CONFIG(CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED)
 static inline int get_global_turbo_state(void)
 {
 	return TURBO_UNKNOWN;

src/cpu/x86/16bit/entry16.inc

@@ -29,8 +29,8 @@
 
 #include <arch/rom_segs.h>
 
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \
-    IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \
+    CONFIG(SIPI_VECTOR_IN_ROM)
 /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
  * Startup IPI message without RAM.
  */
@@ -44,7 +44,7 @@ _start16bit:
 	cli
 	/* Save the BIST result */
 	movl	%eax, %ebp
-#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
+#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
 	post_code(POST_RESET_VECTOR_CORRECT)
 #endif
 

src/cpu/x86/32bit/entry32.inc

@@ -47,7 +47,7 @@ __protected_start:
 	/* Save the BIST value */
 	movl	%eax, %ebp
 
-#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
+#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
 	post_code(POST_ENTER_PROTECTED_MODE)
 #endif
 

src/cpu/x86/backup_default_smm.c

@@ -25,7 +25,7 @@ void *backup_default_smm_area(void)
 	void *save_area;
 	const void *default_smm = (void *)SMM_DEFAULT_BASE;
 
-	if (!IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+	if (!CONFIG(HAVE_ACPI_RESUME))
 		return NULL;
 
 	/*

src/cpu/x86/car.c

@@ -20,7 +20,7 @@
 #include <arch/early_variables.h>
 #include <symbols.h>
 
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
+#if CONFIG(PLATFORM_USES_FSP1_0)
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #endif
 typedef void (* const car_migration_func_t)(void);
@@ -61,7 +61,7 @@ void *car_get_var_ptr(void *var)
 		return var;
 	}
 
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
+#if CONFIG(PLATFORM_USES_FSP1_0)
 	migrated_base = (char *)find_saved_temp_mem(
 			*(void **)CBMEM_FSP_HOB_PTR);
 	/* FSP 1.0 migrates the entire DCACHE RAM */
@@ -96,7 +96,7 @@ void *car_sync_var_ptr(void *var)
 	 * keep console buffer in CAR until cbmemc_reinit() moves it.
 	 */
 	if (*mig_var == _preram_cbmem_console) {
-		if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0))
+		if (CONFIG(PLATFORM_USES_FSP1_0))
 			*mig_var += (char *)mig_var - (char *)var;
 		return mig_var;
 	}
@@ -142,7 +142,7 @@ static void do_car_migrate_variables(void)
 
 static void car_migrate_variables(int is_recovery)
 {
-	if (!IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0))
+	if (!CONFIG(PLATFORM_USES_FSP1_0))
 		do_car_migrate_variables();
 }
 ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables)

src/cpu/x86/lapic/apic_timer.c

@@ -98,7 +98,7 @@ void udelay(u32 usecs)
 	} while ((start - value) < ticks);
 }
 
-#if IS_ENABLED(CONFIG_LAPIC_MONOTONIC_TIMER)
+#if CONFIG(LAPIC_MONOTONIC_TIMER)
 #include <timer.h>
 
 static struct monotonic_counter {

src/cpu/x86/lapic/boot_cpu.c

@@ -15,7 +15,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic_def.h>
 
-#if IS_ENABLED(CONFIG_SMP)
+#if CONFIG(SMP)
 int boot_cpu(void)
 {
 	int bsp;

src/cpu/x86/lapic/lapic_cpu_init.c

@@ -147,9 +147,9 @@ static int lapic_start_cpu(unsigned long apicid)
 		}
 		return 0;
 	}
-#if !IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) \
-	&& !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_206AX) \
-	&& !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_2065X)
+#if !CONFIG(CPU_AMD_MODEL_10XXX) \
+	&& !CONFIG(CPU_INTEL_MODEL_206AX) \
+	&& !CONFIG(CPU_INTEL_MODEL_2065X)
 	mdelay(10);
 #endif
 
@@ -320,7 +320,7 @@ int start_cpu(struct device *cpu)
 	return result;
 }
 
-#if IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT)
+#if CONFIG(AP_IN_SIPI_WAIT)
 
 /**
  * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of
@@ -408,7 +408,7 @@ asmlinkage void secondary_cpu_init(unsigned int index)
 {
 	atomic_inc(&active_cpus);
 
-	if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+	if (!CONFIG(PARALLEL_CPU_INIT))
 		spin_lock(&start_cpu_lock);
 
 #ifdef __SSE3__
@@ -423,7 +423,7 @@ asmlinkage void secondary_cpu_init(unsigned int index)
 #endif
 	cpu_initialize(index);
 
-	if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+	if (!CONFIG(PARALLEL_CPU_INIT))
 		spin_unlock(&start_cpu_lock);
 
 	atomic_dec(&active_cpus);
@@ -440,7 +440,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
 		if (cpu->path.type != DEVICE_PATH_APIC)
 			continue;
 
-		if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
+		if (CONFIG(PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
 			continue;
 
 		if (!cpu->enabled)
@@ -454,7 +454,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
 			printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
 				cpu->path.apic.apic_id);
 
-		if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+		if (!CONFIG(PARALLEL_CPU_INIT))
 			udelay(10);
 	}
 
@@ -554,24 +554,24 @@ void initialize_cpus(struct bus *cpu_bus)
 	if (is_smp_boot())
 		copy_secondary_start_to_lowest_1M();
 
-	if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION))
+	if (!CONFIG(SERIALIZED_SMM_INITIALIZATION))
 		smm_init();
 
 	/* start all aps at first, so we can init ECC all together */
-	if (is_smp_boot() && IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+	if (is_smp_boot() && CONFIG(PARALLEL_CPU_INIT))
 		start_other_cpus(cpu_bus, info->cpu);
 
 	/* Initialize the bootstrap processor */
 	cpu_initialize(0);
 
-	if (is_smp_boot() && !IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+	if (is_smp_boot() && !CONFIG(PARALLEL_CPU_INIT))
 		start_other_cpus(cpu_bus, info->cpu);
 
 	/* Now wait the rest of the cpus stop*/
 	if (is_smp_boot())
 		wait_other_cpus_stop(cpu_bus);
 
-	if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) {
+	if (CONFIG(SERIALIZED_SMM_INITIALIZATION)) {
 		/* At this point, all APs are sleeping:
 		 * smm_init() will queue a pending SMI on all cpus
 		 * and smm_other_cpus() will start them one by one */
@@ -589,7 +589,7 @@ void initialize_cpus(struct bus *cpu_bus)
 		recover_lowest_1M();
 }
 
-#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if !CONFIG(HAVE_SMI_HANDLER)
 /* Empty stubs for platforms without SMI handlers. */
 void smm_init(void)
 {

src/cpu/x86/mp_init.c

@@ -714,7 +714,7 @@ struct mp_state {
 
 static int is_smm_enabled(void)
 {
-	return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && mp_state.do_smm;
+	return CONFIG(HAVE_SMI_HANDLER) && mp_state.do_smm;
 }
 
 static void smm_disable(void)
@@ -724,7 +724,7 @@ static void smm_disable(void)
 
 static void smm_enable(void)
 {
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
+	if (CONFIG(HAVE_SMI_HANDLER))
 		mp_state.do_smm = 1;
 }
 
@@ -891,7 +891,7 @@ static int run_ap_work(struct mp_callback *val, long expire_us)
 	struct stopwatch sw;
 	int cur_cpu = cpu_index();
 
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) {
+	if (!CONFIG(PARALLEL_MP_AP_WORK)) {
 		printk(BIOS_ERR, "APs already parked. PARALLEL_MP_AP_WORK not selected.\n");
 		return -1;
 	}
@@ -933,7 +933,7 @@ static void ap_wait_for_instruction(void)
 	struct mp_callback **per_cpu_slot;
 	int cur_cpu;
 
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK))
+	if (!CONFIG(PARALLEL_MP_AP_WORK))
 		return;
 
 	cur_cpu = cpu_index();
@@ -1028,7 +1028,7 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops)
 	 * Default to smm_initiate_relocation() if trigger callback isn't
 	 * provided.
 	 */
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) &&
+	if (CONFIG(HAVE_SMI_HANDLER) &&
 		ops->per_cpu_smm_trigger == NULL)
 		mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation;
 }