sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/msi/ms7707/devicetree.cb: Align contents

Browse Source 
Change-Id: I2e8100d01d1feb29df83c400f712e58ae9a5e402
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
2020-01-01 21:50:59 +01:00
committed by Nico Huber
parent 026fd87f39
commit cd57d576eb
1 changed files with 30 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/msi/ms7707/devicetree.cb
View File

@@ -16,6 +16,11 @@ chip northbridge/intel/sandybridge
end end
device domain 0x0 on device domain 0x0 on
subsystemid 0x1462 0x7707 inherit subsystemid 0x1462 0x7707 inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 off end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065" register "c2_latency" = "0x0065"
register "docking_supported" = "0" register "docking_supported" = "0"
@@ -27,13 +32,14 @@ chip northbridge/intel/sandybridge
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "gpe0_en" = "0x28000040" register "gpe0_en" = "0x28000040"
device pci 16.0 on end # Management Engine Interface 1 device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2 device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT device pci 16.3 off end # Management Engine KT
device pci 19.0 on end # Intel Gigabit Ethernet device pci 19.0 on end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2 device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio Audio controller device pci 1b.0 on end # HD Audio controller
device pci 1c.0 on end # PCIe Port #1 device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2 device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3 device pci 1c.2 off end # PCIe Port #3
@@ -44,7 +50,7 @@ chip northbridge/intel/sandybridge
device pci 1c.7 off end # PCIe Port #8 device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1 device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge PCI-LPC bridge device pci 1f.0 on # LPC bridge
chip superio/fintek/f71808a chip superio/fintek/f71808a
register "multi_function_register_0" = "0x00" # 0x28 register "multi_function_register_0" = "0x00" # 0x28
register "multi_function_register_1" = "0xc0" # 0x29 register "multi_function_register_1" = "0xc0" # 0x29
@@ -109,8 +115,5 @@ chip northbridge/intel/sandybridge
device pci 1f.5 off end # SATA Controller 2 device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 off end # Thermal device pci 1f.6 off end # Thermal
end end
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 off end # Internal graphics
end end
end end