mb/msi/ms7707/devicetree.cb: Align contents
Change-Id: I2e8100d01d1feb29df83c400f712e58ae9a5e402 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@@ -16,6 +16,11 @@ chip northbridge/intel/sandybridge
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end
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device domain 0x0 on
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subsystemid 0x1462 0x7707 inherit
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 02.0 off end # Internal graphics
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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@@ -27,13 +32,14 @@ chip northbridge/intel/sandybridge
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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register "gpe0_en" = "0x28000040"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 on end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio Audio controller
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device pci 1b.0 on end # HD Audio controller
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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@@ -44,7 +50,7 @@ chip northbridge/intel/sandybridge
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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device pci 1f.0 on # LPC bridge
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chip superio/fintek/f71808a
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register "multi_function_register_0" = "0x00" # 0x28
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register "multi_function_register_1" = "0xc0" # 0x29
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@@ -109,8 +115,5 @@ chip northbridge/intel/sandybridge
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 off end # Thermal
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end
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 02.0 off end # Internal graphics
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end
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end
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