soc/intel/xeon_sp: Add IIO resources via SSDT

There is no need to inject this code in DSDT. Just generating a _CRS
Name in SSDT containing a resource template works well and reduces the
need to sync up on names being used to return _CRS names in DSDT.

TEST=intel/archercity CRB

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/xeon_sp/acpi/iiostack.asl

@@ -14,11 +14,6 @@
 			}						\
 			Return (\_SB_.PR##rt)				\
 		}							\
-		External(\_SB.RT##id)					\
-		Method (_CRS, 0, NotSerialized)				\
-		{							\
-			Return (\_SB.RT##id)				\
-		}							\
 		Name (SUPP, 0x00)					\
 		Name (CTRL, 0x00)					\
 		Name (_PXM, 0x00)  /* _PXM: Device Proximity */		\

src/soc/intel/xeon_sp/cpx/soc_acpi.c

@@ -41,7 +41,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 	fadt->flags &=  ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE);
 }
 
-void uncore_inject_dsdt(const struct device *device)
+void uncore_fill_ssdt(const struct device *device)
 {
 	struct iiostack_resource stack_info = {0};
 
@@ -51,15 +51,14 @@ void uncore_inject_dsdt(const struct device *device)
 
 	get_iiostack_info(&stack_info);
 
-	acpigen_write_scope("\\_SB");
-
 	for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) {
 		const STACK_RES *ri = &stack_info.res[stack];
 		char rtname[16];
 
-		snprintf(rtname, sizeof(rtname), "RT%02x", stack);
+		snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", stack);
+		acpigen_write_scope(rtname);
 
-		acpigen_write_name(rtname);
+		acpigen_write_name("_CRS");
 		printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n",
 			rtname, stack);
 
@@ -106,8 +105,10 @@ void uncore_inject_dsdt(const struct device *device)
 			(ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
 
 		acpigen_write_resourcetemplate_footer();
+
+		/* Scope */
+		acpigen_pop_len();
 	}
-	acpigen_pop_len();
 }
 
 /* TODO: See if we can use the common generate_p_state_entries */

src/soc/intel/xeon_sp/include/soc/acpi.h

@@ -20,7 +20,7 @@ typedef struct {
 
 unsigned long northbridge_write_acpi_tables(const struct device *device,
 	unsigned long current, struct acpi_rsdp *rsdp);
-void uncore_inject_dsdt(const struct device *device);
+void uncore_fill_ssdt(const struct device *device);
 unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current);
 unsigned long acpi_fill_cedt(unsigned long current);
 unsigned long acpi_fill_hmat(unsigned long current);

src/soc/intel/xeon_sp/skx/soc_acpi.c

@@ -54,7 +54,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 	fill_fadt_extended_pm_io(fadt);
 }
 
-void uncore_inject_dsdt(const struct device *device)
+void uncore_fill_ssdt(const struct device *device)
 {
 	const IIO_UDS *hob = get_iio_uds();
 
@@ -62,7 +62,6 @@ void uncore_inject_dsdt(const struct device *device)
 	if (device->bus->secondary != 0)
 		return;
 
-	acpigen_write_scope("\\_SB");
 	for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) {
 		if (!soc_cpu_is_enabled(socket))
 			continue;
@@ -72,10 +71,12 @@ void uncore_inject_dsdt(const struct device *device)
 		for (int stack = 0; stack <= PSTACK2; ++stack) {
 			const STACK_RES *ri = &iio_resource.StackRes[stack];
 			char rtname[16];
-			snprintf(rtname, sizeof(rtname), "RT%02x",
-				(socket*MAX_IIO_STACK)+stack);
 
-			acpigen_write_name(rtname);
+			snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", socket * MAX_IIO_STACK + stack);
+			acpigen_write_scope(rtname);
+
+			acpigen_write_name("_CRS");
+
 			printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n",
 				rtname, socket, stack);
 
@@ -126,9 +127,11 @@ void uncore_inject_dsdt(const struct device *device)
 				(ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
 
 			acpigen_write_resourcetemplate_footer();
+
+			/* Scope */
+			acpigen_pop_len();
 		}
 	}
-	acpigen_pop_len();
 }
 
 void soc_power_states_generation(int core, int cores_per_package)

src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl

@@ -26,11 +26,6 @@ Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET, STACK))
 	{
 		Return (\_SB.PRTID)
 	}
-	External (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK))
-	Method (_CRS, 0, NotSerialized)
-	{
-		Return (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK))
-	}
 	Name (SUPP, 0x00) // PCI _OSC Support Field Value
 	Name (CTRL, 0x00) // PCI _OSC Control Field Value
 	Name (SUPC, 0x00) // CXL _OSC Support Field Value

src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl

@@ -5,30 +5,20 @@
 
 #undef DEVPREFIX
 #define DEVPREFIX  DI
-#undef RESPREFIX
-#define RESPREFIX  DT
 #include "pci_resource.asl"
 
 #undef DEVPREFIX
 #define DEVPREFIX  PM
-#undef RESPREFIX
-#define RESPREFIX  MT
 #include "pci_resource.asl"
 
 #undef DEVPREFIX
 #define DEVPREFIX  HQ
-#undef RESPREFIX
-#define RESPREFIX  HT
 #include "pci_resource.asl"
 
 #undef DEVPREFIX
 #define DEVPREFIX  PN
-#undef RESPREFIX
-#define RESPREFIX  MU
 #include "pci_resource.asl"
 
 #undef DEVPREFIX
 #define DEVPREFIX  HR
-#undef RESPREFIX
-#define RESPREFIX  HU
 #include "pci_resource.asl"

src/soc/intel/xeon_sp/spr/acpi/iiostack.asl

@@ -3,8 +3,6 @@
 /* ***** PCI Stacks **** */
 #undef DEVPREFIX
 #define DEVPREFIX  PC
-#undef RESPREFIX
-#define RESPREFIX  PT
 #undef STPREFIX
 #define STPREFIX   ST
 
@@ -39,8 +37,6 @@
 /* ***** CXL Stacks **** */
 #undef DEVPREFIX
 #define DEVPREFIX  CX
-#undef RESPREFIX
-#define RESPREFIX  CT
 
 #undef STACK
 #define STACK 1

src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl

@@ -22,11 +22,6 @@ Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET, STACK))
 	{
 		Return (\_SB.PRTID)
 	}
-	External (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK))
-	Method (_CRS, 0, NotSerialized)
-	{
-		Return (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK))
-	}
 	Name (SUPP, 0x00)
 	Name (CTRL, 0x00)
 	Name (_PXM, SOCKET)  /* _PXM: Device Proximity */

src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl

@@ -5,8 +5,6 @@
 
 #undef DEVPREFIX
 #define DEVPREFIX  UC
-#undef RESPREFIX
-#define RESPREFIX  UT
 #include "pci_resource.asl"
 
 #undef PRTID
@@ -14,6 +12,4 @@
 
 #undef DEVPREFIX
 #define DEVPREFIX  UD
-#undef RESPREFIX
-#define RESPREFIX  UU
 #include "pci_resource.asl"

src/soc/intel/xeon_sp/spr/soc_acpi.c

@@ -62,11 +62,11 @@ static void create_dsdt_iou_pci_resource(uint8_t socket, uint8_t stack, const ST
 	   Stacks 1 .. 5 (TYPE_UBOX_IIO)
 		Scope: PC<socket><stack>, ResourceTemplate: RBRS
 	*/
-
+	/* write _CRS scope */
-	/* Write ResourceTemplate resource name */
 	char tres[16];
-	snprintf(tres, sizeof(tres), "PT%d%X", socket, stack);
+	snprintf(tres, sizeof(tres), "\\_SB.PC%d%X", socket, stack);
-	acpigen_write_name(tres);
+	acpigen_write_scope(tres);
+	acpigen_write_name("_CRS");
 
 	printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres,
 	       socket, stack);
@@ -133,6 +133,7 @@ static void create_dsdt_iou_pci_resource(uint8_t socket, uint8_t stack, const ST
 	}
 
 	acpigen_write_resourcetemplate_footer();
+	acpigen_pop_len();
 }
 
 static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
@@ -141,10 +142,11 @@ static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const ST
 	   Stacks 1 .. 5 (TYPE_UBOX_IIO)
 		Scope: CX<socket><stack>, ResourceTemplate: RBRS
 	*/
-	/* write ResourceTemplate resource name */
+	/* write _CRS scope */
 	char tres[16];
-	snprintf(tres, sizeof(tres), "CT%d%X", socket, stack);
+	snprintf(tres, sizeof(tres), "\\_SB.CX%d%X", socket, stack);
-	acpigen_write_name(tres);
+	acpigen_write_scope(tres);
+	acpigen_write_name("_CRS");
 
 	printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres,
 	       socket, stack);
@@ -184,6 +186,7 @@ static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const ST
 	}
 
 	acpigen_write_resourcetemplate_footer();
+	acpigen_pop_len();
 }
 
 static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
@@ -222,32 +225,32 @@ static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK
 			mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE
 				     + CPM_MMIO_SIZE + HQM_MMIO_SIZE;
 			mem64_limit = ri->PciResourceMem64Limit;
-			snprintf(tres, sizeof(tres), "DT%d%X", socket, stack);
+			snprintf(tres, sizeof(tres), "\\_SB.DI%d%X", socket, stack);
 		} else if (rlist[i] == DSDT_CPM) {
 			bus_base = ri->BusBase + CPM_BUS_OFFSET;
 			bus_limit = bus_base + CPM_RESERVED_BUS;
 			mem64_base = ri->PciResourceMem64Base;
 			mem64_limit = mem64_base + CPM_MMIO_SIZE - 1;
-			snprintf(tres, sizeof(tres), "MT%d%X", socket, stack);
+			snprintf(tres, sizeof(tres), "\\_SB.PM%d%X", socket, stack);
 		} else if (rlist[i] == DSDT_HQM) {
 			bus_base = ri->BusBase + HQM_BUS_OFFSET;
 			bus_limit = bus_base + HQM_RESERVED_BUS;
 			mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE;
 			mem64_limit = mem64_base + HQM_MMIO_SIZE - 1;
-			snprintf(tres, sizeof(tres), "HT%d%X", socket, stack);
+			snprintf(tres, sizeof(tres), "\\_SB.HQ%d%X", socket, stack);
 		} else if (rlist[i] == DSDT_CPM1) {
 			bus_base = ri->BusBase + CPM1_BUS_OFFSET;
 			bus_limit = bus_base + CPM_RESERVED_BUS;
 			mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE;
 			mem64_limit = mem64_base + CPM_MMIO_SIZE - 1;
-			snprintf(tres, sizeof(tres), "MU%d%X", socket, stack);
+			snprintf(tres, sizeof(tres), "\\_SB.PN%d%X", socket, stack);
-		} else { // DSDT_HQM1
+		} else {
 			bus_base = ri->BusBase + HQM1_BUS_OFFSET;
 			bus_limit = bus_base + HQM_RESERVED_BUS;
 			mem64_base = ri->PciResourceMem64Base + CPM_MMIO_SIZE + HQM_MMIO_SIZE
 				     + CPM_MMIO_SIZE;
 			mem64_limit = mem64_base + HQM_MMIO_SIZE - 1;
-			snprintf(tres, sizeof(tres), "HU%d%X", socket, stack);
+			snprintf(tres, sizeof(tres), "\\_SB.HR%d%X", socket, stack);
 		}
 
 		/* Note, some SKU doesn't provide CPM1 and HQM1 and owns smaller bus ranges
@@ -260,7 +263,8 @@ static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK
 		       "stack: %d\n bus_base:0x%x, bus_limit:0x%x\n",
 		       tres, socket, stack, bus_base, bus_limit);
 
-		acpigen_write_name(tres);
+		acpigen_write_scope(tres);
+		acpigen_write_name("_CRS");
 		acpigen_write_resourcetemplate_header();
 
 		acpigen_resource_word(2, 0xc, 0, 0, bus_base, bus_limit, 0x0,
@@ -278,6 +282,7 @@ static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK
 			(mem64_limit - mem64_base + 1));
 
 		acpigen_write_resourcetemplate_footer();
+		acpigen_pop_len();
 	}
 }
 
@@ -287,19 +292,19 @@ static void create_dsdt_ubox_resource(uint8_t socket, uint8_t stack, const STACK
 	   Stacks D .. E (TYPE_UBOX)
 		Scope: UC/UD<socket><0..1> for UBOX[1-2], ResourceTemplate: UT/UU
 	*/
-
 	for (int i = 0; i < 2; ++i) {
 		char tres[16];
-		/* write ResourceTemplate resource name */
+		/* write _CRS scope */
 		if (i == 0)
-			snprintf(tres, sizeof(tres), "UT%d%X", socket, stack);
+			snprintf(tres, sizeof(tres), "\\_SB.UC%d%X", socket, stack);
 		else
-			snprintf(tres, sizeof(tres), "UU%d%X", socket, stack);
+			snprintf(tres, sizeof(tres), "\\_SB.UD%d%X", socket, stack);
 
 		printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n",
 		       tres, socket, stack);
 
-		acpigen_write_name(tres);
+		acpigen_write_scope(tres);
+		acpigen_write_name("_CRS");
 		acpigen_write_resourcetemplate_header();
 
 		if (!stack_enabled)
@@ -311,6 +316,7 @@ static void create_dsdt_ubox_resource(uint8_t socket, uint8_t stack, const STACK
 					      0x0, 1);
 
 		acpigen_write_resourcetemplate_footer();
+		acpigen_pop_len();
 	}
 }
 
@@ -330,7 +336,7 @@ static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, const STACK_RES
 		acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_ON);
 }
 
-void uncore_inject_dsdt(const struct device *device)
+void uncore_fill_ssdt(const struct device *device)
 {
 	bool stack_enabled;
 
@@ -354,8 +360,6 @@ void uncore_inject_dsdt(const struct device *device)
 
 	printk(BIOS_DEBUG, "%s device: %s\n", __func__, dev_path(device));
 
-	acpigen_write_scope("\\_SB");
-
 	/* The _CSR generation must match SPR iiostack.asl. */
 	const IIO_UDS *hob = get_iio_uds();
 	/* Iterate over CONFIG_MAX_SOCKET to keep ASL templates and DSDT injection in sync */
@@ -383,8 +387,6 @@ void uncore_inject_dsdt(const struct device *device)
 			}
 		}
 	}
-
-	acpigen_pop_len();
 }
 
 /* TODO: See if we can use the common generate_p_state_entries */

src/soc/intel/xeon_sp/uncore.c

@@ -349,7 +349,7 @@ static struct device_operations mmapvtd_ops = {
 	.init              = mmapvtd_init,
 	.ops_pci           = &soc_pci_ops,
 #if CONFIG(HAVE_ACPI_TABLES)
-	.acpi_inject_dsdt  = uncore_inject_dsdt,
+	.acpi_fill_ssdt  = uncore_fill_ssdt,
 #endif
 };