soc/intel: Use common romstage code

This provides stack guards with checking and common
entry into postcar.

The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.

Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/include/cpu/intel/romstage.h

@@ -1,14 +0,0 @@
-#ifndef _CPU_INTEL_ROMSTAGE_H
-#define _CPU_INTEL_ROMSTAGE_H
-
-#include <arch/romstage.h>
-
-void mainboard_romstage_entry(void);
-
-/* fill_postcar_frame() is called after raminit completes and right before
- * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr()
- * to tag memory ranges as cacheable to speed up execution of postcar and
- * early ramstage. */
-void fill_postcar_frame(struct postcar_frame *pcf);
-
-#endif /* _CPU_INTEL_ROMSTAGE_H */