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soc/intel: Use common romstage code

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This provides stack guards with checking and common
entry into postcar.

The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.

Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-17 20:51:08 +03:00
parent 16248e89ec
commit cd7a70f487
56 changed files with 133 additions and 201 deletions
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19
src/soc/intel/baytrail/romstage/romstage.c
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@@ -54,23 +54,6 @@
static struct postcar_frame early_mtrrs;
static void fill_postcar_frame(struct postcar_frame *pcf);
/* prepare_and_run_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
static void prepare_and_run_postcar(struct postcar_frame *pcf)
{
if (postcar_frame_init(pcf, 0))
die("Unable to initialize postcar frame.\n");
fill_postcar_frame(pcf);
postcar_frame_common_mtrrs(pcf);
run_postcar_phase(pcf);
/* We do not return here. */
}
static void program_base_addresses(void)
{
uint32_t reg;
@@ -260,7 +243,7 @@ void romstage_common(struct romstage_params *params)
romstage_handoff_init(prev_sleep_state == ACPI_S3);
}
static void fill_postcar_frame(struct postcar_frame *pcf)
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;