intel/apollolake: Update gnvs for dptf

This patch updates dptf variable in gnvs based on device
configuration by reading the device tree structure.

BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
       under /sys/class/thermal in Amenia and Reef board.
       Navigate to /sys/class/thermal, and verify that a
       thermal zone of type TCPU exists there.

Change-Id: I8ab34cdc94d8cdc840b02347569a9f07688e92cd
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15620
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/chip.h

@@ -102,6 +102,9 @@ struct soc_intel_apollolake_config {
 
 	/* Configure LPSS S0ix Enable */
 	uint8_t lpss_s0ix_enable;
+
+	/* Enable DPTF support */
+	int dptf_enable;
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */