From cdf99a9b3e2550d2be9dd7c2940ac081ac8eb8e8 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Thu, 29 Sep 2022 12:24:53 +0200 Subject: [PATCH] soc/rockchip/rk3288/clock.c: Remove trailing semicolon Signed-off-by: Elyes Haouas Change-Id: I0d03bd43b33570ee50f145ea6fd716c4072a11d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67965 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/rockchip/rk3288/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 1576a6a2bf..c2f93f5854 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -53,7 +53,7 @@ static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ - "divisors on line " STRINGIFY(__LINE__)); + "divisors on line " STRINGIFY(__LINE__)) /* Keep divisors as low as possible to reduce jitter and power usage. */ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);