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mb/purism/librem_cnl: Use chipset dt reference names

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Use the references from the chipset devicetree as this makes the
comments superfluous.

Change-Id: I87cec9026bcb621ceb7eae51f65ae35bc31d584a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
This commit is contained in:
Felix Singer
2024-01-18 07:22:34 +01:00
committed by Felix Singer
parent 185ff285f6
commit ce391cd426
3 changed files with 65 additions and 65 deletions
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98
src/mainboard/purism/librem_cnl/devicetree.cb
View File

@@ -44,58 +44,58 @@ chip soc/intel/cannonlake
device cpu_cluster 0 on end device cpu_cluster 0 on end
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device ref system_agent on end
device pci 02.0 on end # Integrated Graphics Device device ref igpu on end
device pci 04.0 on # SA Thermal device device ref dptf on
register "Device4Enable" = "1" register "Device4Enable" = "1"
end end
device pci 12.0 on end # Thermal Subsystem device ref thermal on end
device pci 13.0 off end # Integrated Sensor Hub device ref ish off end
device pci 14.0 on end # USB xHC device ref xhci on end
device pci 14.1 off end # USB xDCI (OTG) device ref xdci off end
device pci 15.0 off end # I2C #0 device ref i2c0 off end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 off end # I2C #2 device ref i2c2 off end
device pci 15.3 off end # I2C #3 device ref i2c3 off end
device pci 16.0 off end # Management Engine Interface 1 device ref heci1 off end
device pci 16.1 off end # Management Engine Interface 2 device ref heci2 off end
device pci 16.2 off end # Management Engine IDE-R device ref csme_ider off end
device pci 16.3 off end # Management Engine KT Redirection device ref csme_ktr off end
device pci 16.4 off end # Management Engine Interface 3 device ref heci3 off end
device pci 16.5 off end # Management Engine Interface 4 device ref heci4 off end
device pci 17.0 on end # SATA device ref sata on end
device pci 19.0 off end # I2C #4 device ref i2c4 off end
device pci 19.1 off end # I2C #5 device ref i2c5 off end
device pci 19.2 off end # UART #2 device ref uart2 off end
device pci 1a.0 off end # eMMC device ref emmc off end
device pci 1c.0 off end # PCI Express Port 1 device ref pcie_rp1 off end
device pci 1c.1 off end # PCI Express Port 2 device ref pcie_rp2 off end
device pci 1c.2 off end # PCI Express Port 3 device ref pcie_rp3 off end
device pci 1c.3 off end # PCI Express Port 4 device ref pcie_rp4 off end
device pci 1c.4 off end # PCI Express Port 5 device ref pcie_rp5 off end
device pci 1c.5 off end # PCI Express Port 6 device ref pcie_rp6 off end
device pci 1c.6 off end # PCI Express Port 7 device ref pcie_rp7 off end
device pci 1c.7 off end # PCI Express Port 8 device ref pcie_rp8 off end
device pci 1d.0 off end # PCI Express Port 9 device ref pcie_rp9 off end
device pci 1d.1 off end # PCI Express Port 10 device ref pcie_rp10 off end
device pci 1d.2 off end # PCI Express Port 11 device ref pcie_rp11 off end
device pci 1d.3 off end # PCI Express Port 12 device ref pcie_rp12 off end
device pci 1d.4 off end # PCI Express Port 13 device ref pcie_rp13 off end
device pci 1d.5 off end # PCI Express Port 14 device ref pcie_rp14 off end
device pci 1d.6 off end # PCI Express Port 15 device ref pcie_rp15 off end
device pci 1d.7 off end # PCI Express Port 16 device ref pcie_rp16 off end
device pci 1e.0 off end # UART #0 device ref uart0 off end
device pci 1e.1 off end # UART #1 device ref uart1 off end
device pci 1e.2 off end # GSPI #0 device ref gspi0 off end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
device pci 1f.0 on end # LPC Bridge device ref lpc_espi on end
device pci 1f.1 off end # P2SB device ref p2sb off end
device pci 1f.2 hidden end # Power Management Controller device ref pmc hidden end
device pci 1f.3 on # Intel HDA device ref hda on
register "PchHdaAudioLinkHda" = "1" register "PchHdaAudioLinkHda" = "1"
end end
device pci 1f.4 on end # SMBus device ref smbus on end
device pci 1f.5 on end # PCH SPI device ref fast_spi on end
device pci 1f.6 off end # GbE device ref gbe off end
end end
end end

20
src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
View File

@@ -24,7 +24,7 @@ chip soc/intel/cannonlake
# Actual device tree # Actual device tree
device domain 0 on device domain 0 on
device pci 02.0 on # Integrated Graphics Device device ref igpu on
register "gfx" = "GMA_DEFAULT_PANEL(0)" register "gfx" = "GMA_DEFAULT_PANEL(0)"
register "panel_cfg" = "{ register "panel_cfg" = "{
.up_delay_ms = 200, .up_delay_ms = 200,
@@ -35,7 +35,7 @@ chip soc/intel/cannonlake
.backlight_off_delay_ms = 1, .backlight_off_delay_ms = 1,
}" }"
end end
device pci 14.0 on # USB xHCI device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -131,8 +131,8 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-C left register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-C left
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader
end end
device pci 14.1 off end # USB xDCI (OTG) device ref xdci off end
device pci 15.0 on # I2C #0 device ref i2c0 on
chip drivers/i2c/hid chip drivers/i2c/hid
register "generic.hid" = ""HTIX5288"" register "generic.hid" = ""HTIX5288""
register "generic.name" = ""TPD0"" register "generic.name" = ""TPD0""
@@ -142,7 +142,7 @@ chip soc/intel/cannonlake
device i2c 2c on end device i2c 2c on end
end end
end end
device pci 17.0 on # SATA device ref sata on
register "satapwroptimize" = "1" register "satapwroptimize" = "1"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
# Port 2 (M.2 / inner) # Port 2 (M.2 / inner)
@@ -152,7 +152,7 @@ chip soc/intel/cannonlake
register "SataPortsEnable[2]" = "1" register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1" register "SataPortsDevSlp[2]" = "1"
end end
device pci 1c.6 on # PCI Express Port 7 -- x1 M.2/E 2230 (WLAN) device ref pcie_rp7 on # x1 M.2/E 2230 (WLAN)
register "PcieRpEnable[6]" = "1" register "PcieRpEnable[6]" = "1"
register "PcieRpSlotImplemented[6]" = "1" register "PcieRpSlotImplemented[6]" = "1"
register "PcieRpLtrEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1"
@@ -161,13 +161,13 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[2]" = "2"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end end
device pci 1c.7 on # PCI Express Port 8 device ref pcie_rp8 on
device pci 00.0 on end # x1 (LAN) device pci 00.0 on end # x1 (LAN)
register "PcieRpEnable[7]" = "1" register "PcieRpEnable[7]" = "1"
register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[3]" = "3"
end end
device pci 1d.0 on # PCI Express Port 9 -- x4 M.2/M 2280 (NVMe) device ref pcie_rp9 on # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[8]" = "1" register "PcieRpEnable[8]" = "1"
register "PcieRpSlotImplemented[8]" = "1" register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpLtrEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1"
@@ -175,7 +175,7 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[0]" = "0"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end end
device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[12]" = "1" register "PcieRpEnable[12]" = "1"
register "PcieRpSlotImplemented[12]" = "1" register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpLtrEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1"
@@ -183,7 +183,7 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end end
device pci 1f.0 on # LPC Bridge device ref lpc_espi on
# LPC configuration from lspci -s 1f.0 -xxx # LPC configuration from lspci -s 1f.0 -xxx
# Address 0x88: Decode 0x68 - 0x6F (EC PM channel) # Address 0x88: Decode 0x68 - 0x6F (EC PM channel)
register "gen1_dec" = "0x00040069" register "gen1_dec" = "0x00040069"

12
src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
View File

@@ -20,7 +20,7 @@ chip soc/intel/cannonlake
# Actual device tree # Actual device tree
device domain 0 on device domain 0 on
device pci 14.0 on # USB xHCI device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -123,12 +123,12 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
end end
device pci 17.0 on # SATA device ref sata on
register "SataPortsEnable[0]" = "1" # 2.5" register "SataPortsEnable[0]" = "1" # 2.5"
register "SataPortsEnable[2]" = "1" # m.2 register "SataPortsEnable[2]" = "1" # m.2
register "satapwroptimize" = "1" register "satapwroptimize" = "1"
end end
device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN) device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN)
register "PcieRpSlotImplemented[7]" = "1" register "PcieRpSlotImplemented[7]" = "1"
register "PcieRpEnable[7]" = "1" register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1"
@@ -136,13 +136,13 @@ chip soc/intel/cannonlake
register "PcieClkSrcUsage[2]" = "0x80" register "PcieClkSrcUsage[2]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end end
device pci 1d.1 on # PCI Express Port 10 device ref pcie_rp10 on
device pci 00.0 on end # x1 (LAN) device pci 00.0 on end # x1 (LAN)
register "PcieRpEnable[9]" = "1" register "PcieRpEnable[9]" = "1"
register "PcieClkSrcUsage[3]" = "9" register "PcieClkSrcUsage[3]" = "9"
register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[3]" = "3"
end end
device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
register "PcieRpSlotImplemented[12]" = "1" register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpEnable[12]" = "1" register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1"
@@ -150,7 +150,7 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end end
device pci 1f.0 on # LPC Bridge device ref lpc_espi on
chip superio/ite/it8528e chip superio/ite/it8528e
device pnp 2e.1 on # UART1 device pnp 2e.1 on # UART1
io 0x60 = 0x3F8 io 0x60 = 0x3F8